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參數(shù)資料
| 型號(hào)： | S1C63466F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP8-144 |
| 文件頁數(shù)： | 18/135頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | S1C63466F |
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106
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
Stopwatch timer
(1) When data of the counter is read at run mode, perform the reading after suspending the counter once
and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976
sec (1/4 cycle of 256 Hz).
(2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen-
cies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function.
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec
(when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of
the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to the
PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is decremented
(-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually stops.
Figure 5.2.1 shows the timing chart for the RUN/STOP control.
PTRUN0/PTRUN1 (WR)
PTD0X/PTD1X
42H
41H 40H 3FH 3EH
3DH
PTRUN0/PTRUN1 (RD)
Input clock
"1" (RUN)
writing
"0" (STOP)
writing
Fig. 5.2.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned ON and OFF by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
Serial interface
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is halted
(i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
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