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參數(shù)資料
| 型號(hào)： | S1C63455D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC105 |
| 封裝： | DIE-105 |
| 文件頁(yè)數(shù)： | 50/119頁(yè) |
| 文件大?。?/td> | 865K |
| 代理商： | S1C63455D |
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28
EPSON
S1C63455 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the
input ports K00–K03, and can specify the terminals for generating interrupt and interrupt timing.
The interrupt selection registers (SIK00–SIK03) select what input of K00–K03 to use for the interrupt.
Writing "1" into an interrupt selection register incorporates that input port into the interrupt generation
conditions. The changing the input port where the interrupt selection register has been set to "0" does not
affect the generation of the interrupt.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that
it be generated at the falling edge according to the set value of the input comparison registers (KCP00–
KCP03).
By setting these two conditions, the interrupt for K00–K03 is generated when input ports in which an
interrupt has been enabled by the input selection registers and the contents of the input comparison
registers have been changed from matching to no matching.
The interrupt mask registers (EIK0) enable the interrupt mask to be selected for K00–K03.
When the interrupt is generated, the interrupt factor flag (IK0) is set to "1".
Figure 4.4.2.2 shows an example of an interrupt for K00–K03.
Interrupt selection register
SIK03
1
SIK02
1
SIK01
1
SIK00
0
Input port
(1)
(Initial value)
Interrupt generation
K03
1
K02
0
K01
1
K00
0
Input comparison register
KCP03
1
KCP02
0
KCP01
1
KCP00
0
With the above setting, the interrupt of K00–K03 is generated under the following condition:
(2)
K03
1
K02
0
K01
1
K00
1
(3)
K03
0
K02
0
K01
1
K00
1
(4)
K03
0
K02
1
K01
1
K00
1
Because K00 interrupt is set to disable, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
comparison register KCP01–KCP03.
Fig. 4.4.2.2 Example of interrupt of K00–K03
K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at
(2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the
data of the input comparison registers, so that interrupt occurs. As already explained, the condition for
the interrupt to occur is the change in the port data and contents of the input comparison registers from
matching to no matching. Hence, in (4), when the no matching status changes to another no matching
status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect
the conditions for interrupt generation.
4.4.3 Mask option
Internal pull-up resistor can be selected for each of the four bits of the input ports (K00–K03) with the
input port mask option.
When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With
pull-up resistor" for input ports that are not being used.
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