
100
Rev. 1.0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M306H1SFP
Figure 2.11.9 UARTi -related registers (6)
UART2 special mode register 2 (I2C bus exclusive register)
Symbol
Address
When reset
U2SMR2
037616
0016
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
STAC
SWC2
SDHI
I C mode selection bit 2
SCL wait output bit
0 : Disabled
1 : Enabled
SDA output stop bit
UART2 initialization bit
Clock-synchronous bit
Refer to Table 2.11.11
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS
0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
2
SHTC
Start/stop condition
control bit
Set this bit to "1" in I2C mode
(refer to Table 2.11.12)
UART2 special mode register 3 (I2C bus exclusive register)
Symbol
Address
When reset
U2SMR3
037516
Indeterminate
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
Function
(I2C bus exclusive)
SDA digital delay value
setting bit
b7 b6 b5
DL0
DL1
DL2
(initializing value is "0016" at SDDS = "1")
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
“0” is read out when SDDS = 1.
W
R
Notes 1: Reading and writing is possible when bit7 (SDDS = SDA digital delay selection
bit) of UART2 special mode register (U2SMR/address 037716) is "1". When
set SDDS = "1" and read out initialized value of UART2 special mode register
3(U2SMR3), this value is "0016".When set SDDS = "1" and write to UART2
special mode register 3(U2SMR3), set "0" to bit 0 to bit 4. When SDDS = "0",
writing is enable. When read out, this value is indeterminate.
2: When SDDS = "0" , this bit is initialized and become "000", selected analog
delay circuit. This bit is become "000" after end reset released, and selected
analog delay circuit. Reading out is possible when only SDDS = "1". when
SDDS = "0", value which was read out is indeterminate.
3: Delaying ; Only analog delay value when analog delay is selected, and only
digital delay value when digital delay is selected.
4: Delay level depends on SCL pin and SDA pin. And, when use external clock,
delay is increase around 100ns. So test first, and use this.
0 0 0 : Analog delay
0 0 1 : 2 cycle of 1/f (Xin)(Digital delay)
0 1 0 : 3 cycle of 1/f (Xin)(Digital delay)
0 1 1 : 4 cycle of 1/f (Xin)(Digital delay)
1 0 0 : 5 cycle of 1/f (Xin)(Digital delay)
1 0 1 : 6 cycle of 1/f (Xin)(Digital delay)
1 1 0 : 7 cycle of 1/f (Xin)(Digital delay)
1 1 1 : 8 cycle of 1/f (Xin)(Digital delay)