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參數(shù)資料
| 型號： | S1C63455D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC105 |
| 封裝： | DIE-105 |
| 文件頁數(shù)： | 37/119頁 |
| 文件大?。?/td> | 865K |
| 代理商： | S1C63455D |
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16
EPSON
S1C63455 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (b) I/O memory map (FF45H–FF71H)
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF45H
PUL13
PUL12
PUL11
PUL10
R/W
PUL13
PUL12
PUL11
PUL10
1
On
Off
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 pull-up control register (ESIF=0)
SIN pull-up control register when SIF is selected
FF46H
P13
P12
P11
P10
R/W
P13
P12
P11
P10
– 2
High
Low
P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
FF60H
LDUTY1 LDUTY0 VCCHG LPWR
R/W
LDUTY1
LDUTY0
VCCHG
LPWR
0
1
VC2
On
0
VC1
Off
General-purpose register
LCD regulated voltage switch
LCD power On/Off
0
Light
–
15
Dark
[LC3–0]
Contrast
FF61H
EXLCDC ALOFF
ALON
LPAGE
R/W
EXLCDC
ALOFF
ALON
LPAGE
0
1
0
1
All Off
All On
1
0
Normal
0
General-purpose register
LCD all OFF control
LCD all ON control
General-purpose register
FF62H
LC3
LC2
LC1
LC0
R/W
LC3
LC2
LC1
LC0
– 2
LCD contrast adjustment
0
4096.0
1
3276.8
2
2730.7
3
2340.6
[BZFQ2, 1, 0]
Frequency (Hz)
4
2048.0
5
1638.4
6
1365.3
7
1170.3
[BZFQ2, 1, 0]
Frequency (Hz)
FF6EH
0
BZFQ2
BZFQ1
BZFQ0
RR/W
0 3
BZFQ2
BZFQ1
BZFQ0
– 2
0
Unused
Buzzer
frequency
selection
FF6FH
0
BDTY2
BDTY1
BDTY0
RR/W
0 3
BDTY2
BDTY1
BDTY0
– 2
0
Unused
Buzzer signal duty ratio selection
(refer to main manual)
FF6CH
ENRTM ENRST
ENON
BZE
R/W
W
R/W
ENRTM
ENRST3
ENON
BZE
0
Reset
0
1 sec
Reset
On
Enable
0.5 sec
Invalid
Off
Disable
Envelope releasing time
Envelope reset (writing)
Envelope On/Off
Buzzer output enable
FF6DH
0
BZSTP BZSHT SHTPW
RW
R/W
0 3
BZSTP3
BZSHT
SHTPW
– 2
0
Stop
Trigger
Busy
125 msec
Invalid
Ready
31.25 msec
Unused
1-shot buzzer stop (writing)
1-shot buzzer trigger (writing)
1-shot buzzer status (reading)
1-shot buzzer pulse width setting
FF70H
0
SCTRG
ESIF
RR/W
0 3
SCTRG
ESIF
– 2
0
Trigger
Run
SIF
Invalid
Stop
I/O
Unused
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
0
Slave
2
OSC1/2
1
PT
3
OSC1
[SCS1, 0]
Clock
[SCS1, 0]
Clock
FF71H
SDP
SCPS
SCS1
SCS0
R/W
SDP
SCPS
SCS1
SCS0
0
MSB first LSB first Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
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