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參數(shù)資料
| 型號： | S1C63455D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC105 |
| 封裝： | DIE-105 |
| 文件頁數(shù)： | 3/119頁 |
| 文件大小： | 865K |
| 代理商： | S1C63455D |
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
99
Rev. 1.0
M306H1SFP
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
UART1 internal/external clock select bit (bit 3 at address 03A8 16) = “0”.
UART transmit/receive control register 2
Symbol
Address
When reset
UCON
03B016
X00000002
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
Reserved bit
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
CLK/CLKS select
bit 1 (Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
UART2 special mode register
Symbol
Address
When reset
U2SMR
037716
0016
b7 b6 b5 b4 b3 b2 b1
b0
Bit name
Bit
symbol
Function
(During clock synchronous
serial I/O mode)
ABSCS
ACSE
SSS
I2C mode selection bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected
SCLL sync output
enable bit
Bus collision detect
sampling
clock select bit
Arbitration lost detecting
flag control bit
0 : Normal mode
1 : I2C mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
LSYN
0 : Disabled
1 : Enabled
Transmit start condition
select bit
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0
Must always be “0”
SDDS
SDA digital delay
selection bit
(Notes 2 and 3)
W
R
Function
(During UART mode)
0 : Ordinary
1 : Falling edge of RxD2
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
Must always be “0”
0 : Analog delay output
selection
1 : Digital delay output selection
(Note 1)
Notes 1: Nothing but "0" may be written.
2: Do not write "1" except at I 2C mode. Must always be “0” at normal mode.
Bit 7 to bit5 (DL2 to DL0 = SDA digital delay value setting bit) of UART2 special mode
register 3 (U2SMR3/address 0375 16) are initialized and become “000” when this bit is "0", analog
delay circuit is selected. Reading and writing U2SMR are enable when SDDS = "0" .
3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value
when digital delay is selected.
Figure 2.11.8 UARTi I/O-related registers (5)
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相關代理商/技術參數(shù) |
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| S1C63616 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63632 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63653 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
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