參數(shù)資料
型號: S-35390A-T8T1
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: REAL TIME CLOCK, PDSO8
封裝: TSSOP-8
文件頁數(shù): 37/48頁
文件大小: 542K
代理商: S-35390A-T8T1
34
EPSON
S1C88816 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
The interrupt selection registers SIK00–SIK03,
SIK04–SIK07 and SIK10 and input comparison
registers KCP00–KCP03, KCP04–KCP07 and KCP10
for each port are used to set the interrupt genera-
tion condition described above.
Input port interrupt can be permitted or prohibited
by the setting of the interrupt selection register SIK.
In contrast to the interrupt enable register EK
which masks the interrupt factor for each series of
terminals, the interrupt selection register SIK is
masks the bit units.
The input comparison register KCP selects whether
the interrupt for each input port will be generated
on the rising edge or the falling edge of input.
When the data content of the input terminals in
which interrupt has been permitted by the interrupt
selection register SIK and the data content of the
input comparison register KCP change from a
conformity state to a non-conformity state, the
interrupt factor flag FK should be set to "1" and an
interrupt is generated.
Figure 5.4.3.2 shows an example of interrupt
generation in the series of terminals K0L (K00–K03).
Because interrupt has been prohibited for K00 by
the interrupt selection register SIK00, with the
settings as shown in (2), an interrupt will not be
generated.
Since K03 is "0" in the next settings (3) in the figure,
the non-conformity between the input terminal
data K01–K03 where interrupt is permitted and the
data from the input comparison registers KCP01–
KCP03 generates an interrupt.
In line with the explanation above, since the change
in the contents of input data and input comparison
registers KCP from a conformity state to a non-
conformity state introduces an interrupt generation
condition, switching from one non-conformity state
to another, as is the case in (4) in the figure, will not
generate an interrupt. Consequently, in order to be
able to generate a second interrupt, either the input
terminal must be returned to a state where its
content is once again in conformity with that of the
input comparison register KCP, or the input
comparison register KCP must be reset.
Input terminals for which interrupt is prohibited
will not influence an interrupt generation condi-
tion.
Interrupt is generated in exactly the same way in
the other two series of terminals K0H (K04–K07)
and K1 (K10).
SIK03
SIK01
11
SIK02
1
SIK00
0
Interrupt selection register
KCP03
KCP01
11
KCP02
0
KCP00
0
Input comparison register
With the settings shown above, interrupt of K0L (K00–K03) is generated under the condition shown below.
K03
K01
11
K02
0
K00
0
Input port
(1)
K03
K01
11
K02
0
K00
1
(2)
K03
K01
01
K02
0
K00
1
(3)
K03
K01
01
K02
1
K00
1
(4)
(Initial values)
→ Interrupt generation
Because interrupt has been prohibited for K00, interrupt will be generated
when non-conformity occurs between the contents of the three bits
K01–K03 and the three bits input comparison register KCP01–KCP03.
Fig. 5.4.3.2 Interrupt generation example in K0L (K00–K03)
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