參數(shù)資料
型號(hào): S-35390A-T8T1
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, PDSO8
封裝: TSSOP-8
文件頁(yè)數(shù): 10/48頁(yè)
文件大?。?/td> 542K
代理商: S-35390A-T8T1
10
EPSON
S1C88816 TECHNICAL MANUAL
3 CPU AND MEMORY CONFIGURATION
3 CPU AND MEMORY CONFIGURATION
In this section, we will explain the CPU and memory configuration.
3.1 CPU
The S1C88816 utilize the S1C88 8-bit core CPU
whose resistor configuration, command set, etc. are
virtually identical to other units in the family of
processors incorporating the S1C88.
See the "S1C88 Core CPU Manual" for the S1C88.
The S1C88816 supports Model 3/minimum mode
of the S1C88 CPU which allows accessing of the
internal memory mapped within the physical space
from 000000H to 01FFFFH.
3.2 Internal Memory
The S1C88816 is equipped with internal ROM and
RAM as shown in Figure 3.2.1.
3.2.1 ROM
The internal ROM capacity is shown below.
Capacity: 116K bytes
Address: 000000H to 00CFFFH
010000H to 01FFFFH
3.2.2 RAM
The internal ROM capacity is shown below.
Capacity: 8K bytes
Address: 00D800H to 00F7FFH
3.2.3 I/O memory
A memory mapped I/O method is employed in the
S1C88816 for interfacing with internal peripheral
circuit. Peripheral circuit control bits and data
register are arranged in data memory space.
Control and data exchange are conducted via
normal memory access. The I/O memory is
arranged from address 00FF00H to address
00FFFFH. See Section 5.1, "I/O Memory Map", for
details of the I/O memory.
3.2.4 Display memory
The S1C88816 is equipped with an internal display
memory which stores a display data for LCD
driver.
The display memory is arranged from address
00F800H to address 00FD57H (including the
unused area). See Section 5.11, "LCD Controller",
for details of the display memory.
3.3 Exception Processing Vectors
Address 000000H to address 000027H in the
program area of the S1C88816 is assigned as
exception processing vectors. Furthermore, from
address 00002AH to address 0000FFH, software
interrupt vectors are assignable to any two bytes
which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they
correspond.
Fig. 3.2.1 Internal memory map
01FFFFH
010000H
00FFFFH
00FF00H
00FD57H
00F800H
00F7FFH
00D800H
00D7FFH
00D200H
00D1FFH
00D100H
00D0FFH
00D000H
00CFFFH
000000H
ROM
(64K bytes)
I/O memory
Display memory
RAM (8K bytes)
Unused area
Melody note RAM
Melody scale RAM
ROM
(52K bytes)
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