參數(shù)資料
型號: S-35390A-T8T1
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: REAL TIME CLOCK, PDSO8
封裝: TSSOP-8
文件頁數(shù): 13/48頁
文件大?。?/td> 542K
代理商: S-35390A-T8T1
12
EPSON
S1C88816 TECHNICAL MANUAL
4 INITIAL RESET
4.1.1 RESET terminal
Initial reset can be done by executed externally
inputting a LOW level to the RESET terminal.
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset.
In addition, be sure to use the RESET terminal for
the first initial reset after the power is turned on.
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
RESET terminal pull-up resistors
RESET ..... s
s With resistor s
s Gate direct
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is to
input a LOW level simultaneously to the input ports
(K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for two seconds (when the oscillation
frequency fOSC1 = 32.768 kHz) or more to perform
the initial reset by means of this function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
Multiple key entry reset
s
s Not use
s
s K00 & K01
s
s K00 & K01 & K02
s
s K00 & K01 & K02 & K03
4 INITIAL RESET
Initial reset in the S1C88816 is required in order to initialize circuits. This chapter describes initial
reset factors and the initial settings for internal registers.
4.1 Initial Reset Factors
There are three initial reset factors for the S1C88816
as shown below.
(1) RESET terminal
(2) Simultaneous LOW level input at input port
terminals K00–K03
(3) Supply voltage detection (SVD) circuit
Figure 4.1.1 shows the configuration of the initial
reset circuit.
The CPU and peripheral circuits are initialized by
means of initial reset factors. When the factor is
canceled, the CPU commences reset exception
processing. (See "S1C88 Core CPU Manual".)
When this occurs, reset exception processing
vectors, Bank 0, 000000H–000001H from program
memory are read out and the program (initializa-
tion routine) which begins at the readout address is
executed.
K00
Input port K00
K01
Input port K01
K02
Input port K02
K03
Input port K03
VDD
RESET
VDD
SLEEP status
Time authorize
circuit
Oscillation stability waiting signal
Internal initial reset
Mask option
Supply voltage detection
(SVD) circuit
Fig. 4.1.1 Configuration of initial reset circuit
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