參數(shù)資料
型號(hào)： RXC101
廠商： RF Monolithics, Inc.
英文描述： Multi-channel High data rate Programmable
中文描述： 多通道可編程數(shù)據(jù)率高
文件頁(yè)數(shù)： 3/33頁(yè)
文件大?。?/td> 546K
代理商： RXC101
3
1. Pin Description
Processor Mode
Pin
1
2
Name
SDI
SCK
Description
SPI Data In
SPI Data Clock
Chip Select Input
– Selects the chip for an SPI data transaction. The pin must be pulled ‘low’
for a 16-bit read or write function. See Figure 6 for timing specifications.
FIFO Interrupt Output (active low)
– When the internal FIFO is enabled (
Configuration
Register,
Bit [6]), this pin acts as a FIFO Fill interrupt indicating that the FIFO has filled to its
pre-programmed limit (
FIFO Configuration Register
, Bit [7..4]).
SPI Serial Data Out
– May be used to read out the
Status Register
contents.
Interrupt Request Output
– Any of the following events will generate an external interrupt:
-Wake-up timer timeout
-Low Battery Detect
-FIFO fill
-FIFO overflow
To determine the source of the interrupt, the processor may read the first four bits of the
Status Register
.
Data Output
– Received data can be taken from this pin when the FIFO is not used.
FIFO Select Input
– When the FIFO is used this pin selects the FIFO when data is to be read
out over the SDO pin.
Data Recovery Clock
Output
– Recovered Data clock Output (FIFO not used).
Filter Capacitor
– When the analog filter is used this pin is the connection for the RC
lowpass filter. The corner frequency should be set as close to the data rate as possible to
retain good sensitivity.
FIFO Interrupt Output (active high)
– Indicates when there are remaining bits in the FIFO to
be read. Set the FIFO Fill level to 1 in the
FIFO Configuration Register
.
Optional host processor Clock Output. Frequency programmable through the
Battery Detect
Threshold and Clock Output Register.
Xtal
- Connects to a 10MHz series crystal or an external oscillator reference.
The circuit
contains an integrated load capacitor (See
Configuration Register
) in order to minimize the
external component count. The crystal is used as the reference for the PLL, which generates
the local oscillator frequency. The accuracy requirements for production tolerance,
temperature drift and aging can be determined from the maximum allowable local oscillator
frequency error. Whenever a low frequency error is essential for the application, it is possible
to “pull” the crystal to the accurate frequency by changing the load capacitor value.
Ext Ref
– An external reference, such as an oscillator, may be connected as a reference
source. Connect through a .01uF capacitor.
Reset Output
(active Low)
System Ground
RF Diff I/O
RF Diff I/O
Supply Voltage
Analog RSSI Output
– This pin may be used as an input to an A/D for signal strength or may
be used as a baseband data output for OOK signaling. See
Baseband Filter Register
to
calculate the appropriate filter capacitor value.
Valid Data Detector Output
- (See
Receiver Control Register
for output definition)
3
nCS
4
nFINT/SDO
5
nIRQ
6
DATA/nFSEL
7
DCLK/FCAP/
FINT
8
ClkOut
9
Xtal/Ref
10
11
12
13
14
nRST
GND
RF_P
RF_N
VDD
15
RSSIA
16
1.1 Processor Mode Pin Configuration
DDET
SDI
SCK
nCS
SDO/FINT
IRQ
DATA/nFSEL
CR/FINT/FCAP
CLKOUT
DDET
RSSIA
VDD
RF_N
RF_P
GND
nRESET
Xtal/Ref
TOP VIEW
RXC101
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
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