參數(shù)資料
型號: RXC101
廠商: RF Monolithics, Inc.
英文描述: Multi-channel High data rate Programmable
中文描述: 多通道可編程數(shù)據(jù)率高
文件頁數(shù): 12/33頁
文件大?。?/td> 546K
代理商: RXC101
12
LNA
VCO
PLL
/N
OSC
0 /9 0
+
-
I/Q
DEMOD
ASK
FSK
CONTROL
LOGIC
BATT
DET
SDO/FFIT
nCS
SDI
nIRQ
DATA / nFSEL
CR/FINT/FCAP
CLKOUT
DDET
XTAL/REF
VDD
nRESET
GND
RSSIA
RSSI
R
RF_P
RF_N
3. RXC101 Functional Characteristics
Figure 5. Functional Block Diagram
Input Amplifier (LNA)
The LNA has selectable gain (0dB, -6dB, -14dB, -20dB) which may be useful in an environment with
strong interferers. The LNA has a 250
Ohm differential input impedance (0dB, -14dB) which requires a
matching circuit when connected to 50 Ohm devices. Registers common to the LNA are:
Power Management Register
Receiver Control Register
Baseband Data and Filtering
The baseband receiver has several programmable options that optimize the data link for a wide range of
applications. The programmable functions include:
Receive bandwidth
Receive data rate
Baseband Analog Filter
Baseband Digital Filter
Clock Recovery (CR)
Receive FIFO
Data Quality Detector
The receive bandwidth is programmable from 67 kHz to 400 kHz to accommodate various FSK
modulation deviations as well as fast data rates. If the deviation is known for a given transmitter, the best
results are obtained with a bandwidth at least twice the transmitter FSK deviation.
The receive data rate is programmable from 337bps to 344kbps. An internal prescaler is used to give
better resolution when setting up the receive data rate. The prescaler is optional and may be disabled
through the
Data Rate Setup Register.
The type of baseband filtering is selectable between an Analog filter and a Digital filter. The analog filter
is a simple RC lowpass filter. An external capacitor may be chosen depending on the actual data rate.
The chip has an integrated 10KOhm resistor in series that makes the RC lowpass network. With the
analog filter selected, a maximum data rate of 256kbps can be achieved. The digital filter is used with a
clock frequency of 29X data rate. In this mode a clock recovery (CR) circuit is used to provide for a
synchronized clock source to recover the data using an external processor. The CR has three modes of
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