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參數(shù)資料
| 型號： | RXC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | Multi-channel High data rate Programmable |
| 中文描述： | 多通道可編程數(shù)據(jù)率高 |
| 文件頁數(shù)： | 28/33頁 |
| 文件大小： | 546K |
| 代理商： | RXC101 |
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28
Duty Cycle Set Register
[POR=CC0Eh]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
1
1
0
0
DC6
DC5
DC4
DC3
DC2
DC1
DC0
DCEN
The duty cycle register may be used in conjunction with the wake-up timer to reduce the average current
consumption of the receiver. The duty cycle register may be set up so that when the wake-up timer
brings the chip out of sleep mode the receiver is turned on for a short time to sample if a signal is present
and then goes back into sleep and the process starts over.
The duty cycle uses the Multiplier value of the wake-up timer in part for its calculation. To calculate the
duty cycle use:
Duty Cycle = ((D[6..0] * 2 )+ 1)/M * 100
where M is M[7..0] of the Wake-up Timer Period register.
Bit [15..8] –
Command Code:
These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Wake-up Timer Period register.
Bit [7..1] –
Duty Cycle Multiplier:
These bits are the decimal value used to calculate the Duty Cycle or
“On time” of the Receiver after the wake-up timer has brought the RXC101 out of sleep mode.
Bit [0] –
Duty Cycle Mode Enable:
This bit enables the duty cycle mode when set.
NOTE:
The receiver must be disabled (RXEN bit 7 cleared in Power Management Register) and the
wake-up timer must be enabled (WKUPEN bit 1 set in Power Management Register) for operation in this
mode.
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