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參數(shù)資料
| 型號： | RXC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | Multi-channel High data rate Programmable |
| 中文描述： | 多通道可編程數(shù)據(jù)率高 |
| 文件頁數(shù)： | 16/33頁 |
| 文件大?。?/td> | 546K |
| 代理商： | RXC101 |
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16
4. Control and Configuration Registers
Status Register
(
Read Only
)
Bit
Bit
Bit
Bit
15
14
13
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
FIFOIT
FIFOV
WKINT
LB
FIFEMP
RSSI GDQD
CRLCK
AFATGL
AFA
OFFSGN
OFF4
OFF3
OFF2
OFF1
OFF0
The Status Register provides feedback for:
FIFO overwrite
FIFO fill interrupt
Low Battery
Data Quality
Digital RSSI signal level
Clock Recovery
Frequency Offset value and sign
AFA
Note:
The Status Register read command begins with a logic ‘0’ where all other register commands begin
with a logic ‘1’.
Bit [15]:
FIFOIT
– When set, indicates that the number of data bits received by the FIFO has reached it
programmed limit. See
FIFO Fill Bit Count Bits[7..4]
of the
FIFO Configuration
Register.
Bit [14]:
FIFOV
– When set, indicates receive FIFO overflow. (Cleared after Status Reg read).
Bit [13]:
WKINT
– When set, indicates a Wake-up timer overflow. (Cleared after Status Reg read).
Bit [12]:
LB
– When set, indicates the supply voltage is below the preprogrammed limit. See
Battery
Detect Threshold and Clock Output Register.
Bit [11]:
FIFEMP
– When set, indicates receive FIFO is empty.
Bit [10]:
RSSI
– When set, this bit indicates that the incoming RF signal is above the preprogrammed
Digital RSSI limit.
Bit [9]:
GDQD
– When set, indicates good data quality.
Bit [8]:
CRLCK
– When set, indicates Clock Recovery is locked.
Bit [7]:
AFATGL
– For each AFA cycle run, this bit will toggle between logic ‘1’ and logic ‘0’.
Bit [6]:
AFA
– When set, indicates that the frequency adjust has detected the same offset value for two
consecutive measurements and thus the frequency is stabilized.
Bit [5]:
OFFSGN
– Indicates the difference in frequency is higher (logic ‘1’) or lower (logic ‘0’) than the chip
frequency.
Bit [4..0]:
OFF[4..0]
– The offset value to be added to the frequency control word (internal PLL).
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