參數(shù)資料
型號(hào)： RXC101
廠商： RF Monolithics, Inc.
英文描述： Multi-channel High data rate Programmable
中文描述： 多通道可編程數(shù)據(jù)率高
文件頁(yè)數(shù)： 19/33頁(yè)
文件大小： 546K
代理商： RXC101
19
Receiver Control Register
[POR=C0C1h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
VDI1
VDI0
GAIN1
GAIN0
RSSI2
RSSI1
RSSI0
RXEN
The Receiver Control Register configures the following:
Receiver LNA gain
Digital RSSI threshold
Receive baseband bandwidth
Valid Data Indicator response time
Function of pin 16
Bit [15..8] –
Command Code:
These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Receiver Control Register.
Bit [7..6] –
Pin 16 Func:
Selects the function of Pin 16. See Table 7 below.
Table 7.
Bit [5..4] –
Receiver LNA Gain:
These bits set the receiver LNA gain, which can be changed to
accommodate environments with high interferers. The LNA gain also affects the true RSSI value.
Refer to Bit [2..0] for RSSI. See Table 8 below for gain configuration.
Table 8.
Bit [3..1] –
Digital RSSI Threshold:
The digital receive signal strength indicator threshold may be set to
indicate that the incoming signal strength is above a preset limit. The result is stored in bit 7 of
the status register. There are eight (8) predefined thresholds that can be set. See Table 9 below
for settings.
Table 9.
Pin 16 Function
Digital RSSI Out
DQD Out
Clock Recovery Lock
Valid Data Output
VDI1
0
0
1
1
VDI0
0
1
0
1
LNA GAIN (dB)
0
-14
-6
-20
GAIN1
0
0
1
1
GAIN0
0
1
0
1
RSSI Thresh
-103
-97
-91
-85
-79
-73
-67
-61
RSSI2
0
0
0
0
1
1
1
1
RSSI1
0
0
1
1
0
0
1
1
RSSI0
0
1
0
1
0
1
0
1
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