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參數(shù)資料
| 型號： | RXC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | Multi-channel High data rate Programmable |
| 中文描述： | 多通道可編程數(shù)據(jù)率高 |
| 文件頁數(shù)： | 11/33頁 |
| 文件大?。?/td> | 546K |
| 代理商： | RXC101 |
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11
The Control Byte function is defined as follows:
Output Function
NOP
Set to Logic ‘0’
Toggle
Set to logic ‘1’ for 100ms
The data section of the packet must be sent as indicated. The 1’s complement of the data is internally
verified against the actual incoming data to ensure it is receiving the correct data and not spurious
transmission from noise or a nearby interferer. By sending the data twice, once before and once after the
1’s complement, this confirms to the receiver that it is receiving valid data.
Duty Cycle Mode
After power-up, connecting pin 8 to VDD will enable duty cycle mode. In this mode the chip will wake up
every 300ms to sample the signal strength of the incoming signal. If there is none detected then it goes
back into sleep until the next 300ms window arrives. When operating in Duty Cycle Mode, the chip
consumes less than 500uA of average current.
From start to finish, when the wake-up timer expires and the chip comes out of sleep, it switches on the
oscillator and waits 2ms for the oscillator to stabilize then it switches on the synthesizer. The receiver
then monitors the incoming signal strength for 6ms. If it detects a signal within that 6ms the synthesizer
remains on for 30ms and waits for the preamble and the rest of the packet. If it does not detect a strong
enough signal within the 6ms, it goes back into sleep mode until the next wake-up time. If it detects a
strong signal, but incorrect data, at the end of the 30ms it will re-enter sleep mode until the next wake-up
time. It should be noted that when the receiver is checking for signal strength, the state of the FS0 pin
will determine the threshold limit. See NOTE after Table 1. Figure 4 shows the timing for Duty Cycle
Mode.
Table 3.
CB(1)
0
0
1
1
CB(0)
0
1
0
1
Figure 4. Duty Cycle Mode Wake-up Timing
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