參數資料
型號： RC28F128P33T85
廠商： NUMONYX
元件分類： PROM
英文描述： 8M X 16 FLASH 3V PROM, 85 ns, PBGA64
封裝： BGA-64
文件頁數： 70/96頁
文件大小： 1378K
代理商： RC28F128P33T85
Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
72
Order Number: 314749-05
Figure 36: BEFP Flowchart
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing ).
BEFP Exit
Repeat for subsequent blocks ;
After BEFP exit, a full Status Register check can
determine if any program error occurred ;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state .
Standby
Read
Bus
State
Operation
Status
Register
Check
Exit
Status
Com ments
Data = Status Register Data
Address = 1st Word Addr.
Check SR [7]:
0 = Exit Not Completed
1 = Exit Completed
BEFP Setup
Com ments
Bus
State
Operation
Write
(Note 1)
BEFP
Setup
Write
BEFP
Confirm
Read
Status
Register
Standby
BEFP
Setup
Done?
Write
Unlock
Block
Data = 0x80 @ 1st Word
Address
Data = 0x80 @ 1st Word
Address
1
Data = Status Register Data
Address = 1st Word Addr.
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
VPPH applied to VPP
Standby
Error
Condition
Check
If SR[7] is set, check:
SR[3] set = VPP Error
SR[1] set = Locked Block
No (SR [0]=1)
Write Data @ 1st
Word Address
Last
Data?
Write 0xFFFF,
Address Not within
Current Block
Program
Done?
Read
Status Reg.
Yes (SR[0]=0)
Y
No (SR[7]=0)
Full Status Check
Procedure
Program
Complete
Read
Status Reg.
BEFP
Exited?
Yes (SR[7]=1)
Start
Write 80h @
1st Word Address
VPP applied
Block Unlocked
Write D0h @
1st Word Address
BEFP Setup
Done?
Read
Status Reg.
No (SR[7]=1)
Exit
N
Program & Verify Phase
Exit Phase
Setup Phase
BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE
Check
X = 32?
Initialize Count:
X = 0
Increment Count:
X = X+1
Y
N
Check VPP, Lock
errors (SR[3,1])
Yes (SR[7]=0)
BEFP Setup delay
Data Stream
Ready?
Read
Status Reg.
Yes (SR[0]=0)
No (SR[0]=1)
BEFP Program & Verify
Com ments
Bus
State
Write
(note 2)
Load
Buffer
Standby
Increment
Count
Standby
Initialize
Count
Data = Data to Program
Address = 1st Word Addr.
X = X+1
X = 0
Read
Status
Register
Standby
Program
Done?
Data = Status Reg. Data
Address = 1st Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
Write
Exit Prog &
Verify Phase
Data = 0xFFFF @ address
not in current block
Standby
Last
Data?
No = Fill buffer again
Yes = Exit
Standby
Buffer
Full?
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Read
Standby
Status
Register
Data Stream
Ready?
Data = Status Register Data
Address = 1st Word Addr.
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Operation
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