參數(shù)資料
型號(hào): PSD4256G6
廠商: 意法半導(dǎo)體
英文描述: Current Mode PWM Controller 16-SOIC 0 to 70
中文描述: Flash在系統(tǒng)可編程ISP的周邊的16位微控制器
文件頁(yè)數(shù): 89/100頁(yè)
文件大小: 759K
代理商: PSD4256G6
89/100
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 66. READ Timing
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. Any input used to select an internal PSD function.
3. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
4. RD timing has the same timing as DS, LDS, and UDS signals.
Symbol
Parameter
Conditions
-10
Turbo
Off
Unit
Min
Max
t
LVLX
ALE or AS Pulse Width
22
ns
t
AVLX
Address Setup Time
(Note
2
)
7
ns
t
LXAX
Address Hold Time
(Note
2
)
8
ns
t
AVQV
Address Valid to Data Valid
2.7 <
V
CC
< 3.6V
(Note
2
)
100
+ 20
ns
3.0 <
V
CC
< 3.6V
(Note
2
)
90
+ 20
ns
t
SLQV
CS Valid to Data Valid
100
ns
t
RLQV
RD to Data Valid
(Note
3
)
35
ns
RD or PSEN to Data Valid on
80C51XA
45
ns
t
RHQX
RD Data Hold Time
(Note
1
)
0
ns
t
RLRH
RD Pulse Width
36
ns
t
RHQZ
RD to Data High-Z
(Note
1
)
38
ns
t
EHEL
E Pulse Width
38
ns
t
THEH
R/W Setup Time to Enable
10
ns
t
ELTL
R/W Hold Time After Enable
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note
3
)
35
ns
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