參數(shù)資料
型號: PSD4256G6
廠商: 意法半導體
英文描述: Current Mode PWM Controller 16-SOIC 0 to 70
中文描述: Flash在系統(tǒng)可編程ISP的周邊的16位微控制器
文件頁數(shù): 21/100頁
文件大?。?/td> 759K
代理商: PSD4256G6
21/100
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 13. Input Macrocells - Ports A, B, and C
Note: Bit Definitions (Read only registers):
READ Input Macrocell (IMC7-IMC0) status on Ports A, B, and C.
Table 14. Output Macrocells A Register
Note: Bit Definitions:
WRITE Register: Load MCellA7-MCellA0 with ’0’ or ’1.’
READ Register: Read MCellA7-MCellA0 output status.
Table 15. Out Macrocells B Register
Note: Bit Definitions:
WRITE Register: Load MCellB7-MCellB0 with ’0’ or ’1.’
READ Register: Read MCellB7-MCellB0 output status.
Table 16. Mask Macrocells A Register
Note: Bit Definitions:
McellA<i>_Prot
0 = Allow MCellA<i> flip-flop to be loaded by MCU (default).
McellA<i>_Prot
1 = Prevent MCellA<i> flip-flop from being loaded by MCU.
Table 17. Mask Macrocells B Register
Note: Bit Definitions:
McellB<i>_Prot
0 = Allow MCellB<i> flip-flop to be loaded by MCU (default).
McellB<i>_Prot
1 = Prevent MCellB<i> flip-flop from being loaded by MCU.
Table 18. Flash Memory Protection Register 1
Note: Bit Definitions (Read only register):
Sec<i>_Prot
1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot
0 = Primary Flash memory Sector <i> is not write protected.
Table 19. Flash Memory Protections Register 2
Note: Bit Definitions (Read only register):
Sec<i>_Prot
1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot
0 = Primary Flash memory Sector <i> is not write protected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec15_Prot
Sec14_Prot
Sec13_Prot
Sec12_Prot
Sec11_Prot
Sec10_Prot
Sec9_Prot
Sec8_Prot
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