參數(shù)資料
型號(hào)： PSD4256G6
廠商： 意法半導(dǎo)體
英文描述： Current Mode PWM Controller 16-SOIC 0 to 70
中文描述： Flash在系統(tǒng)可編程ISP的周邊的16位微控制器
文件頁數(shù)： 42/100頁
文件大?。?/td> 759K
代理商： PSD4256G6
PSD4256G6V
42/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A pins and are named as McellA0-
McellA7. The other eight Macrocells are connect-
ed to Ports B pins and are named as McellB0-
McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15, page 44. As shown in the fig-
ure, there are native product terms available from
the AND Array, and borrowed product terms avail-
able (if unused) from other Output Macrocells
(OMC). The polarity of the product term is con-
trolled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, us-
ing the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path to the
AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft program. The flip-flop’s clock, preset, and
clear inputs may be driven from a product term of
the AND Array. Alternatively, the external CLKIN
(PD1) signal can be used for the clock input to the
flip-flop. The flip-flop is clocked on the rising edge
of CLKIN (PD1). The preset and clear are active
High inputs. Each clear input can use up to two
product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
Note: 1. D7-D0 are used for loading or reading in 8-bit mode.
Output
Macrocell
Port
Assignment
Native Product
Terms
Maximum
Borrowed
Product Terms
16-bit MCU
Loading or
Reading
(1)
Motorola 16-bit
MCU for
Loading or
Reading
McellA0
Port A0
3
6
D0
D8
McellA1
Port A1
3
6
D1
D9
McellA2
Port A2
3
6
D2
D10
McellA3
Port A3
3
6
D3
D11
McellA4
Port A4
3
6
D4
D12
McellA5
Port A5
3
6
D5
D13
McellA6
Port A6
3
6
D6
D14
McellA7
Port A7
3
6
D7
D15
McellB0
Port B0
4
5
D8
D0
McellB1
Port B1
4
5
D9
D1
McellB2
Port B2
4
5
D10
D2
McellB3
Port B3
4
5
D11
D3
McellB4
Port B4
4
6
D12
D4
McellB5
Port B5
4
6
D13
D5
McellB6
Port B6
4
6
D14
D6
McellB7
Port B7
4
6
D15
D7
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