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參數(shù)資料
| 型號(hào)： | PSD4256G6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Current Mode PWM Controller 16-SOIC 0 to 70 |
| 中文描述： | Flash在系統(tǒng)可編程ISP的周邊的16位微控制器 |
| 文件頁數(shù)： | 34/100頁 |
| 文件大?。?/td> | 759K |
| 代理商： | PSD4256G6 |
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PSD4256G6V
34/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
SPECIFIC FEATURES
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft program. This automatically
protects selected sectors when the device is pro-
grammed through the JTAG Port or a Device Pro-
grammer. Flash memory sectors can be
unprotected to allow updating of their contents us-
ing the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
the CSIOP block) or use the READ Sector Protec-
tion instruction. See Table 18, page 21 to Table
20, page 22.
RESET
The RESET instruction consists of one WRITE cy-
cle (see Table 29, page 27). It can also be option-
ally preceded by the standard two WRITE
decoding cycles (writing AAh to AAAh, and 55h to
554h).
The RESET instruction must be executed after:
– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device
has set the Error Flag Bit (DQ5/DQ13) to '1')
during a Flash memory Program or Erase cycle.
The RESET instruction immediately puts the Flash
memory back into normal READ Mode. However,
if there is an error condition (with the Error Flag Bit
(DQ5/DQ13) set to '1') the Flash memory will re-
turn to the READ Mode in 25
μ
s after the RESET
instruction is issued.
The RESET instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The RESET instruction aborts any on-
going Sector Erase cycle, and returns the Flash
memory to the normal READ Mode in 25
μ
s.
Reset (RESET) Pin
A pulse on the Reset (RESET) pin aborts any cy-
cle that is in progress, and resets the Flash mem-
ory to the READ Mode. When the reset occurs
during a Program or Erase cycle, the Flash mem-
ory takes up to 25
μ
s to return to the READ Mode.
It is recommended that the Reset (RESET) pulse
(except for Power On Reset, as described on page
74) be at least 25
μ
s so that the Flash memory is
always ready for the MCU to retrieve the bootstrap
instructions after the RESET cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Standby (V
STBY
, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (V
BATON
, PE7) sig-
nal is High when the supply voltage falls below the
battery voltage and the battery on Voltage Stand-
by (V
STBY
, PE6) is supplying power to the internal
SRAM.
SRAM Select (RS0), Voltage Standby (V
STBY
,
PE6) and Battery-on Indicator (V
BATON
, PE7) are
all configured using PSDsoft.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45_11 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45A-05 | 功能描述:線性和開關(guān)式電源 30W 5Vout 6A Input 9.2-18VDC RoHS:否 制造商:TDK-Lambda 產(chǎn)品:Switching Supplies 開放式框架/封閉式:Enclosed 輸出功率額定值:800 W 輸入電壓:85 VAC to 265 VAC 輸出端數(shù)量:1 輸出電壓（通道 1）:20 V 輸出電流（通道 1）:40 A 商用/醫(yī)用: 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:Rack 長度: 寬度: 高度: |
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