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參數(shù)資料
| 型號： | PSD4256G6 |
| 廠商： | 意法半導體 |
| 英文描述： | Current Mode PWM Controller 16-SOIC 0 to 70 |
| 中文描述： | Flash在系統(tǒng)可編程ISP的周邊的16位微控制器 |
| 文件頁數(shù)： | 38/100頁 |
| 文件大?。?/td> | 759K |
| 代理商： | PSD4256G6 |
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PSD4256G6V
38/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft, the logic is programmed into the
device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12, page 39 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An Input Bus consisting of 82 signals is connected
to the PLDs. The signals are shown in Table 32.
The Turbo Bit in PSD
The PLDs in the PSD4256G6V can minimize pow-
er consumption by switching to standby when in-
puts remain unchanged for an extended time of
about 70ns. Resetting the Turbo Bit to ’0’ (Bit 3 of
the PMMR0 register) automatically places the
PLDs into standby if no inputs are changing. Turn-
ing the Turbo mode off increases propagation de-
lays while reducing power consumption. See the
section entitled “POWER MANAGEMENT”, on
page 70, on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 32. DPLD and CPLD Inputs
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
Input Source
Input Name
Number
of
Signals
MCU Address Bus
(1)
A15-A0
16
MCU Control Signals
CNTL0-CNTL2
3
Reset
RST
1
Power-down
PDN
1
Port A Input
Macrocells
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7-PC0
8
Port D Inputs
PD3-PD0
4
Port F Inputs
PF7-PF0
8
Page Register
PGR7-PGR0
8
Macrocell A Feedback
MCELLA.FB7-FB0
8
Macrocell B Feedback
MCELLB.FB7-FB0
8
Flash memory
Program Status Bit
Ready/Busy
1
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| PSD4256G6V-10UI | 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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