參數(shù)資料
型號： PSD4256G6
廠商： 意法半導(dǎo)體
英文描述： Current Mode PWM Controller 16-SOIC 0 to 70
中文描述： Flash在系統(tǒng)可編程ISP的周邊的16位微控制器
文件頁數(shù)： 74/100頁
文件大小： 759K
代理商： PSD4256G6
PSD4256G6V
74/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RESET TIMING AND DEVICE STATUS AT RESET
Power-on RESET
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
NLNH-PO
(minimum 1ms)
after V
CC
is steady. During this period, the device
loads internal configurations, clears some of the
registers and sets the Flash memory into Operat-
the PSD remains in the RESET Mode for an addi-
tional period, t
OPR
(maximum 120 ns), before the
first memory access is allowed.
The PSD Flash memory is reset to the READ
Mode upon Power-up. Sector Select (FS0-FS15
and CSBOOT0-CSBOOT3) must all be Low,
WRITE Strobe (WR/WRL, CNTL0) High, during
Power-on RESET for maximum security of the
data contents and to remove the possibility of data
being written on the first edge of WRITE Strobe
(WR/WRL, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when
V
CC
is below V
LKO
.
Warm RESET
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t
NLNH
(minimum 150ns). The same t
OPR
period is
needed before the device is operational after
Warm RESET. Figure 34, page 75 shows the tim-
ing of the Power-up and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table 51 shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET and
Power-down mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before the V
CC
ramps up to operat-
ing level. Once the PLD is active, the state of the
outputs are determined by equations specified in
PSDsoft.
RESET of Flash Memory Erase and Program
Cycles
An external Reset (RESET) also resets the inter-
nal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET)
terminates the cycle and returns the Flash memo-
ry to the READ Mode within a period of t
NLNH-A
(minimum 25
μ
s).
Table 51. Status During Power-on RESET, Warm RESET, and Power-down Mode
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to ’0’ on Power-on RESET or Warm RESET.
Port Configuration
Power-on RESET
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to 0
Unchanged
Unchanged
Macrocells Flip-flop status
Cleared to 0 by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register
(1)
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to 0
Cleared to 0
Unchanged
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