參數(shù)資料
型號： PSD211R
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,可加密,19個可單獨配置I/O,通用PLD有12個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，可加密，19個可單獨配置的I / O，通用PLD的有12個輸入）
文件頁數(shù)： 5/32頁
文件大?。?/td> 175K
代理商： PSD211R
PSD211R
2-5
Name
Type
Description
The PSEN is the active low EPROM read pulse. TheI/O ports read
signal is generated according to the description of the WR/V
PP
or
R/W, and RD/E pins. If the host processor is a member of the 8031
family, PSEN must be connected to the corresponding host pin.
In other 8-bit host processors that do not have a special
EPROM-only read strobe, PSEN should be tied to V
CC
. In this case,
RD or E and R/W provide the read strobe for the I/O ports and
EPROM.
PSEN
I
In the operating mode this pin's function is WR (CRRWR = 0) or
R/W (CRRWR = 1). When configured as R/W, the following tables
summarize the read and write operations (CRRWR = 1):
WR/V
PP
or
R/W/V
PP
R/W
X
0
1
E
0
1
1
I
NOP
write
read
When configured as WR, a write operation is executed during an
active low pulse. When configured as R/W, with R/W = 1 and E = 1,
a read operation is executed; if R/W = 0 and E = 1, a write
operation is executed. In programming mode, this pin must be tied
to V
PP
voltage.
When configured as RD (CRRWR = 0), this pin provides an active
low RD strobe. When configured as E (CRRWR = 1), this pin
becomes an active high pulse, which, together with R/W defines the
cycle type. Then, if R/W = 1 and E = 1, a read operation is executed.
If R/W = 0 and E = 1, a write operation is executed.
RD/E
I
This pin has two configurations. When it is CSI (A19/CSI = 0) and
the pin is asserted high, the device is deselected and powered down.
(See Tables 9 and 10 for the chip state during power-down mode.)
If the pin is asserted low, the chip is in normal operational mode.
When it is configured as A19, (A19/CSI = 1), this pin can be used
as an additional input to the PAD. CATD = 1 defines the pin as an
address; CATD = 0 defines it as a logic input. If it is an address,
A19 can be latched with ALE (CADDHLT = 1) or be a transparent
logic input (CADDHLT = 0). In this mode, there is no power-down
capability.
A19/CSI
I
This user-programmable pin can be configured to reset on high
level (CRESET = 1) or on low level (CRESET = 0). It should
remain active for at least 100 ns. See Tables 7 and 8 for reset
details.
RESET
I
The ALE pin functions as an Address Latch Enable or as an Address
strobe and can be configured as an active high or active low signal.
The ALE or AS trailing edge latches lines AD7/A7–AD0/A0 and
A16–A19 depending on the PSD2XX configuration.
ALE
or AS
I
Legend:
The I/O column abbreviations are: I = input; I/O = input/output; P = power.
NOTE
:
1. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in
the Configuration Register section.
Table 1.
PSD211R Pin
Descriptions
相關PDF資料
PDF描述
PSD301-20QI Field-Programmable Peripheral
PSD301-20U 40V 1 Form A Photo Voltaic Relay in a 4-Lead SOP Package; A PVY116 with Standard Packaging
PSD301-20UI Field-Programmable Peripheral
PSD301-20XI Field-Programmable Peripheral
PSD301-20XM 400V 1 Form A Photo Voltaic Relay in a 6-pin SMT Package; A PVT412AS with Tape and Reel Packaging
相關代理商/技術參數(shù)
參數(shù)描述
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