參數(shù)資料
型號: PSD211R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,可加密,19個可單獨配置I/O,通用PLD有12個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,可加密,19個可單獨配置的I / O,通用PLD的有12個輸入)
文件頁數(shù): 15/32頁
文件大?。?/td> 175K
代理商: PSD211R
PSD211R
2-15
Figure 6. Port C Structure
CS8 (OUTPUT LINE)
FROM PAD
TO PAD
A16
CS9 (OUTPUT LINE)
FROM PAD
TO PAD
A17
CS10 (OUTPUT LINE)
FROM PAD
TO PAD
A18
ALE
ADDRESS INDICATOR
(NOTE 7)
TO
EPROM
PC0
PC1
PC2
CATD
ADDRESS
LATCH
ADDRESS
LATCH
CPCF1
CONF.
BIT
ADDRESS
LATCH
CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
CPCF2
CONF.
BIT
CPCF0
CONF.
BIT
NOTES:
7. The CADDHLT configuration bit determines if A18–A16 are transparent via the latch, or if
they must be latched by the trailing edge of the ALE strobe.
8. All Port C pins are either address or logic inputs (CATD).
Port Functions
(cont.)
EPROM
The 32K x 8 EPROM has 8 banks of memory. Each bank is 4K x 8 and can be placed in
any address location by programming the PAD. Bank0–Bank7 is selected by PAD outputs
ES0–ES7, respectively.
A16–A19
Inputs
If one or more of the pins PC0, PC1 PC2 and CSI/A19 are configured as inputs, the
configuration bits CADDHLT and CATD define their functionality inside the part. CADDHLT
determines if these inputs are to be latched by the trailing edge of the ALE or AS signal
(CADDHLT = 1), or enabled into the PSD211R at all times (CADDHLT = 0, transparent
mode). CATD determines whether these lines are high-order address lines, that take part in
the derivation of EPROM select signals inside the chip (CATD = 1), or logic input lines that
have no impact on memory or I/O selections (CATD = 0). Logic input lines typically
participate in the Boolean expressions implemented in the PAD B. Unused input pins
should be tied to V
CC
or GND.
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