參數(shù)資料
型號(hào): PSD211R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,可加密,19個(gè)可單獨(dú)配置I/O,通用PLD有12個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備(可編程邏輯,可加密,19個(gè)可單獨(dú)配置的I / O,通用PLD的有12個(gè)輸入)
文件頁(yè)數(shù): 14/32頁(yè)
文件大?。?/td> 175K
代理商: PSD211R
PSD211R
2-14
Port Functions
(Cont.)
Register Name
Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT
Pin Register of Port A
+ 2 (accessible during read operation only)
Direction Register of Port A
+ 4
Data Register of Port A
+ 6
Pin Register of Port B
+ 3 (accessible during read operation only)
Direction Register of Port B
+ 5
Data Register of Port B
+ 7
Table 6. I/O Port Addresses
Accessing the I/O Port Registers
Table 6 shows the offset values with the respect to the base address defined by the
CSIOPORT. They let the user access the corresponding registers.
Port C
Each pin of Port C (shown in Figure 6) can be configured as an input to PAD A and PAD B
or output from PAD B. As inputs, the pins are named A16–A18. Although the pins are given
names of the high-order address bus, they can be used for any other address lines or logic
inputs to PAD A and PAD B. For example, A8–A10 can also be connected to those pins,
improving the boundaries of CS0–CS7 resolution to 256 bytes. As inputs, they can be
individually configured to be logic or address inputs. A logic input uses the PAD only for
Boolean equations that are implemented in any or all of the CS0–CS10 PAD B outputs. Port
C addresses can be programmed to latch the inputs by the trailing edge ALE or to be
transparent.
Alternately, PC0–PC2 can become CS8–CS10 outputs, respectively, providing the user with
more external chip-select PAD outputs. Each of the signals CS8–CS10 is comprised of one
product term.
相關(guān)PDF資料
PDF描述
PSD301-20QI Field-Programmable Peripheral
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PSD301-20UI Field-Programmable Peripheral
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