參數(shù)資料
型號： PMWD19UN
英文描述： Dual uTrenchMOS (tm) ultra low level FET
中文描述： 雙uTrenchMOS（TM）超低水平場效應管
文件頁數(shù)： 5/12頁
文件大小： 244K
代理商： PMWD19UN
Philips Semiconductors
PMWD19UN
Dual
μ
TrenchMOS ultra low level FET
Product data
Rev. 01 — 20 December 2002
5 of 12
9397 750 10833
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5.
Characteristics
Table 4:
T
j
= 25
°
C unless otherwise specified
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
Characteristics
Conditions
Min
Typ
Max
Unit
I
D
= 250
μ
A; V
GS
= 0 V
T
j
= 25
°
C
T
j
=
55
°
C
I
D
= 1 mA; V
DS
= V
GS;
Figure 9
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°
C
T
j
= 150
°
C
V
GS
=
±
10 V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 3.5 A;
Figure 7
and
8
T
j
= 25
°
C
T
j
= 150
°
C
V
GS
= 1.8 V; I
D
= 3.5 A;
Figure 7
V
GS
= 2.5 V; I
D
= 3.5 A;
Figure 7
30
27
0.45
-
-
0.7
-
-
-
V
V
V
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
-
-
-
-
-
-
-
-
-
-
-
-
19
32
25
21
1
100
100
-
23
39
35
26
μ
A
μ
A
nA
m
m
m
m
m
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
Dynamic characteristics
Q
g(tot)
total gate charge
Q
gs
gate-source charge
Q
gd
gate-drain (Miller) charge
C
iss
input capacitance
C
oss
output capacitance
C
rss
reverse transfer capacitance
t
d(on)
turn-on delay time
t
r
rise time
t
d(off)
turn-off delay time
t
f
fall time
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 4 A; V
GS
= 0 V;
Figure 12
t
rr
reverse recovery time
Q
r
recovered charge
I
D
= 5 A; V
DD
= 16 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
28
2.3
6.1
1478 -
161
128
15
23
56
30
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
GS
= 0 V; V
DS
= 10 V; f = 1 MHz;
Figure 11
-
-
-
-
-
-
V
DD
= 15 V; I
D
= 1 A; V
GS
= 4.5 V; R
G
= 6
-
-
-
0.67
50
19
1.2
-
-
V
ns
nC
I
S
= 4 A; dI
S
/dt =
100 A/
μ
s; V
R
= 30 V;
V
GS
= 0 V
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