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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18F4585-I/P
寤犲晢锛� Microchip Technology
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鏂囦欢澶�?銆�?/td> 0K
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8-bit PIC® Microcontroller Portfolio
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绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
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鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 11x10b
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鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 645 (CN2011-ZH PDF)
閰嶇敤锛� I3-DB18F4680-ND - BOARD DAUGHTER ICEPIC3
DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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PIC18F2585/2680/4585/4680
DS39625C-page 84
Preliminary
2007 Microchip Technology Inc.
B2DLC(8)
Receive mode
鈥�
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
-xxx xxxx
B2DLC(8)
Transmit mode
鈥擳XRTR
鈥�
DLC3
DLC2
DLC1
DLC0
-x-- xxxx
B2EIDL(8)
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
B2EIDH(8)
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
B2SIDL(8)
Receive mode
SID2
SID1
SID0
SRR
EXID
鈥擡ID17
EID16
xxxx x-xx
B2SIDL(8)
Transmit mode
SID2
SID1
SID0
鈥�
EXIDE
鈥擡ID17
EID16
xxx- x-xx
B2SIDH(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
B2CON(8)
Receive mode
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
0000 0000
B2CON(8)
Transmit mode
TXBIF
RXM1
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000
B1D7(8)
B1D77
B1D76
B1D75
B1D74
B1D73
B1D72
B1D71
B1D70
xxxx xxxx
B1D6(8)
B1D67
B1D66
B1D65
B1D64
B1D63
B1D62
B1D61
B1D60
xxxx xxxx
B1D5(8)
B1D57
B1D56
B1D55
B1D54
B1D53
B1D52
B1D51
B1D50
xxxx xxxx
B1D4(8)
B1D47
B1D46
B1D45
B1D44
B1D43
B1D42
B1D41
B1D40
xxxx xxxx
B1D3(8)
B1D37
B1D36
B1D35
B1D34
B1D33
B1D32
B1D31
B1D30
xxxx xxxx
B1D2(8)
B1D27
B1D26
B1D25
B1D24
B1D23
B1D22
B1D21
B1D20
xxxx xxxx
B1D1(8)
B1D17
B1D16
B1D15
B1D14
B1D13
B1D12
B1D11
B1D10
xxxx xxxx
B1D0(8)
B1D07
B1D06
B1D05
B1D04
B1D03
B1D02
B1D01
B1D00
xxxx xxxx
B1DLC(8)
Receive mode
鈥�
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
-xxx xxxx
B1DLC(8)
Transmit mode
鈥擳XRTR
鈥�
DLC3
DLC2
DLC1
DLC0
-x-- xxxx
B1EIDL(8)
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
B1EIDH(8)
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
B1SIDL(8)
Receive mode
SID2
SID1
SID0
SRR
EXID
鈥擡ID17
EID16
xxxx x-xx
B1SIDL(8)
Transmit mode
SID2
SID1
SID0
鈥�
EXIDE
鈥擡ID17
EID16
xxx- x-xx
B1SIDH(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
B1CON(8)
Receive mode
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
0000 0000
B1CON(8)
Transmit mode
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000
B0D7(8)
B0D77
B0D76
B0D75
B0D74
B0D73
B0D72
B0D71
B0D70
xxxx xxxx
B0D6(8)
B0D67
B0D66
B0D65
B0D64
B0D63
B0D62
B0D61
B0D60
xxxx xxxx
B0D5(8)
B0D57
B0D56
B0D55
B0D54
B0D53
B0D52
B0D51
B0D50
xxxx xxxx
B0D4(8)
B0D47
B0D46
B0D45
B0D44
B0D43
B0D42
B0D41
B0D40
xxxx xxxx
B0D3(8)
B0D37
B0D36
B0D35
B0D34
B0D33
B0D32
B0D31
B0D30
xxxx xxxx
B0D2(8)
B0D27
B0D26
B0D25
B0D24
B0D23
B0D22
B0D21
B0D20
xxxx xxxx
B0D1(8)
B0D17
B0D16
B0D15
B0D14
B0D13
B0D12
B0D11
B0D10
xxxx xxxx
B0D0(8)
B0D07
B0D06
B0D05
B0D04
B0D03
B0D02
B0D01
B0D00
xxxx xxxx
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2585/2680/4585/4680) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2:
The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as 鈥�0鈥�. See Section 4.4 鈥淏rown-out Reset
(BOR)鈥�.
3:
These registers and/or bits are not implemented on PIC18F2X8X devices and are read as 鈥�0鈥�. Reset values are shown for PIC18F4X8X
devices; individual unimplemented bits should be interpreted as 鈥樷€斺€�.
4:
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as 鈥�0鈥�. See Section 2.6.4 鈥淧LL in
INTOSC Modes鈥�.
5:
The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as 鈥�0鈥�. This bit is read-only.
6:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as 鈥�0鈥�.
7:
CAN bits have multiple functions depending on the selected mode of the CAN module.
8:
This register reads all 鈥�0鈥檚 until the ECAN technology is set up in Mode 1 or Mode 2.
9:
These registers are available on PIC18F4X8X devices only.
鐩搁棞(gu膩n)PDF璩囨枡
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