[ label ] RRNCF f [,d [,a] Oper" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4585-I/P
寤犲晢锛� Microchip Technology
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鏍稿績铏曠悊鍣細 PIC
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鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 11x10b
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鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 645 (CN2011-ZH PDF)
閰嶇敤锛� I3-DB18F4680-ND - BOARD DAUGHTER ICEPIC3
DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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2002 Microchip Technology Inc.
Preliminary
DS30485A-page 245
PIC18FXX39
RRNCF
Rotate Right f (no carry)
Syntax:
[ label ] RRNCF f [,d [,a]
Operands:
0
鈮� f 鈮� 255
d
鈭� [0,1]
a
鈭� [0,1]
Operation:
(f<n>)
鈫� dest<n-1>,
(f<0>)
鈫� dest<7>
Status Affected:
N, Z
Encoding:
0100
00da
ffff
Description:
The contents of register 'f' are
rotated one bit to the right. If 'd' is 0,
the result is placed in W. If 'd' is 1,
the result is placed back in register
'f' (default). If 鈥榓(ch菐n)鈥� is 0, the Access
Bank will be selected, overriding
the BSR value. If 鈥榓(ch菐n)鈥� is 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
=
1101 0111
After Instruction
REG
=
1110 1011
Example 2:
RRNCF
REG, 0, 0
Before Instruction
W=
?
REG
=
1101 0111
After Instruction
W=
1110 1011
REG
=
1101 0111
register f
SETF
Set f
Syntax:
[ label ] SETF f [,a]
Operands:
0
鈮� f 鈮� 255
a
鈭� [0,1]
Operation:
FFh
鈫� f
Status Affected:
None
Encoding:
0110
100a
ffff
Description:
The contents of the specified regis-
ter are set to FFh. If 鈥榓(ch菐n)鈥� is 0, the
Access Bank will be selected, over-
riding the BSR value. If 鈥榓(ch菐n)鈥� is 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Example:
SETF
REG,1
Before Instruction
REG
=
0x5A
After Instruction
REG
=
0xFF
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
PIC18F4585T-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 48KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4585T-I/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 48KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F458-E/L 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 34 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F458-E/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 34 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F458-E/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 34 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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