PIC18F2585/2680/4585/4680
DS39625C-page 70
Preliminary
2007 Microchip Technology Inc.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The
SFRs
are
typically
distributed
among
the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2585/2680/4585/4680 DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
FFFh
TOSU
FDFh
INDF2(3)
FBFh
CCPR1H
F9Fh
IPR1
FFEh
TOSH
FDEh
POSTINC2(3)
FBEh
CCPR1L
F9Eh
PIR1
FFDh
TOSL
FDDh
POSTDEC2(3)
FBDh
CCP1CON
F9Dh
PIE1
FFCh
STKPTR
FDCh
PREINC2(3)
FBCh
ECCPR1H(1)
F9Ch
—
FFBh
PCLATU
FDBh
PLUSW2(3)
FBBh
ECCPR1L(1)
F9Bh
OSCTUNE
FFAh
PCLATH
FDAh
FSR2H
FBAh
ECCP1CON(1)
F9Ah
—
FF9h
PCL
FD9h
FSR2L
FB9h
—
F99h
—
FF8h
TBLPTRU
FD8h
STATUS
FB8h
BAUDCON
F98h
—
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
ECCP1DEL
F97h
—
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
ECCP1AS(1)
F96h
TRISE(1)
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON(1)
F95h
TRISD(1)
FF4h
PRODH
FD4h
—
FB4h
CMCON
F94h
TRISC
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
HLVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
—
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRGH
F90h
—
FEFh
INDF0(3)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
—
FEEh
POSTINC0(3)
FCEh
TMR1L
FAEh
RCREG
F8Eh
—
FEDh
POSTDEC0(3)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(1)
FECh
PREINC0(3)
FCCh
TMR2
FACh
TXSTA
F8Ch
LATD(1)
FEBh
PLUSW0(3)
FCBh
PR2
FABh
RCSTA
F8Bh
LATC
FEAh
FSR0H
FCAh
T2CON
FAAh
EEADRH
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
EEADR
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
—
FE7h
INDF1(3)
FC7h
SSPSTAT
FA7h
EECON2(3)
F87h
—
FE6h
POSTINC1(3)
FC6h
SSPCON1
FA6h
EECON1
F86h
—
FE5h
POSTDEC1(3)
FC5h
SSPCON2
FA5h
IPR3
F85h
—
FE4h
PREINC1(3)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE(1)
FE3h
PLUSW1(3)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD(1)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
Note
1:
Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2:
When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3:
This is not a physical register.
