PORTE(3) 鈥�
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18F4585-I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 303/322闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU FLASH 24KX16 40DIP
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯欐簴鍖呰锛� 10
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫ｉ€氭€э細 CAN锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孒LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
绋嬪簭瀛樺劜鍣ㄥ閲忥細 48KB锛�24K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 3.25K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 A/D 11x10b
鎸暕鍣ㄥ瀷锛� 鍏ч儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 645 (CN2011-ZH PDF)
閰嶇敤锛� I3-DB18F4680-ND - BOARD DAUGHTER ICEPIC3
DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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2007 Microchip Technology Inc.
Preliminary
DS39625C-page 79
PIC18F2585/2680/4585/4680
PORTE(3)
鈥�
鈥擱E3(5)
RE2(3)
RE1(3)
RE0(3)
---- xxxx
PORTD(3)
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx
PORTB
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx
PORTA
RA7(6)
RA6(6)
Read PORTA pins, Write PORTA Data Latch
xx00 0000
ECANCON
MDSEL1
MDSEL0
FIFOWM
EWIN4
EWIN3
EWIN2
EWIN1
EWIN0
0001 000
TXERRCNT
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
0000 0000
RXERRCNT
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
0000 0000
COMSTAT
Mode 0
RXB0OVFL
RXB1OVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
0000 0000
COMSTAT
Mode 1
鈥�
RXBnOVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
-000 0000
COMSTAT
Mode 2
FIFOEMPTY
RXBnOVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
0000 0000
CIOCON
鈥�
ENDRHI
CANCAP
鈥�
--00 ----
BRGCON3
WAKDIS
WAKFIL
鈥�
SEG2PH2
SEG2PH1
SEG2PH0
00-- -000
BRGCON2
SEG2PHTS
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000 0000
BRGCON1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000 0000
CANCON
Mode 0
REQOP2
REQOP1
REQOP0
ABAT
WIN2(7)
WIN1(7)
WIN0(7)
鈥�(7)
1000 000-
CANCON
Mode 1
REQOP2
REQOP1
REQOP0
ABAT
鈥�(7)
1000 ----
CANCON
Mode 2
REQOP2
REQOP1
REQOP0
ABAT
FP3(7)
FP2(7)
FP1(7)
FP0(7)
1000 0000
CANSTAT
Mode 0
OPMODE2
OPMODE1
OPMODE0
鈥�(7)
ICODE3(7)
ICODE2(7)
ICODE1(7)
鈥�(7)
000- 0000
CANSTAT
Modes 1, 2
OPMODE2
OPMODE1
OPMODE0 EICODE4(7) EICODE3(7)
EICODE2(7)
EICODE1(7)
EICODE0(7)
0000 0000
RXB0D7
RXB0D77
RXB0D76
RXB0D75
RXB0D74
RXB0D73
RXB0D72
RXB0D71
RXB0D70
xxxx xxxx
RXB0D6
RXB0D67
RXB0D66
RXB0D65
RXB0D64
RXB0D63
RXB0D62
RXB0D61
RXB0D60
xxxx xxxx
RXB0D5
RXB0D57
RXB0D56
RXB0D55
RXB0D54
RXB0D53
RXB0D52
RXB0D51
RXB0D50
xxxx xxxx
RXB0D4
RXB0D47
RXB0D46
RXB0D45
RXB0D44
RXB0D43
RXB0D42
RXB0D41
RXB0D40
xxxx xxxx
RXB0D3
RXB0D37
RXB0D36
RXB0D35
RXB0D34
RXB0D33
RXB0D32
RXB0D31
RXB0D30
xxxx xxxx
RXB0D2
RXB0D27
RXB0D26
RXB0D25
RXB0D24
RXB0D23
RXB0D22
RXB0D21
RXB0D20
xxxx xxxx
RXB0D1
RXB0D17
RXB0D16
RXB0D15
RXB0D14
RXB0D13
RXB0D12
RXB0D11
RXB0D10
xxxx xxxx
RXB0D0
RXB0D07
RXB0D06
RXB0D05
RXB0D04
RXB0D03
RXB0D02
RXB0D01
RXB0D00
xxxx xxxx
RXB0DLC
鈥�
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
-xxx xxxx
RXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
RXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
RXB0SIDL
SID2
SID1
SID0
SRR
EXID
鈥擡ID17
EID16
xxxx x-xx
RXB0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
RXB0CON
Mode 0
RXFUL
RXM1
RXM0(7)
鈥�(7)
RXRTRRO(7) RXBODBEN(7)
JTOFF(7)
FILHIT0(7)
000- 0000
RXB0CON
Mode 1, 2
RXFUL
RXM1
RTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
0000 0000
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2585/2680/4585/4680) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2:
The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as 鈥�0鈥�. See Section 4.4 鈥淏rown-out Reset
(BOR)鈥�.
3:
These registers and/or bits are not implemented on PIC18F2X8X devices and are read as 鈥�0鈥�. Reset values are shown for PIC18F4X8X
devices; individual unimplemented bits should be interpreted as 鈥樷€斺€�.
4:
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as 鈥�0鈥�. See Section 2.6.4 鈥淧LL in
INTOSC Modes鈥�.
5:
The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as 鈥�0鈥�. This bit is read-only.
6:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as 鈥�0鈥�.
7:
CAN bits have multiple functions depending on the selected mode of the CAN module.
8:
This register reads all 鈥�0鈥檚 until the ECAN technology is set up in Mode 1 or Mode 2.
9:
These registers are available on PIC18F4X8X devices only.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
PIC18F2680-I/SO IC MCU FLASH 32KX16 28SOIC
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PIC18F8527-I/PT IC PIC MCU FLASH 24KX16 80TQFP
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
PIC18F4585T-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 48KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
PIC18F4585T-I/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 48KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
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