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| 型號(hào)： | PIC17C43 |
| 英文描述： | PIC17C42/42A/43/44/CR42A/CR43 Datasheet |
| 中文描述： | PIC17C42/42A/43/44/CR42A/CR43數(shù)據(jù)表 |
| 文件頁數(shù)： | 62/71頁 |
| 文件大?。?/td> | 1173K |
| 代理商： | PIC17C43 |
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1996 Microchip Technology Inc.
DS30412C-page 65
PIC17C4X
10.0
OVERVIEW OF TIMER
RESOURCES
The PIC17C4X has four timer modules. Each module
can generate an interrupt to indicate that an event has
occurred. These timers are called:
Timer0 - 16-bit timer with programmable 8-bit
prescaler
Timer1 - 8-bit timer
Timer2 - 8-bit timer
Timer3 - 16-bit timer
For enhanced time-base functionality, two input Cap-
tures and two Pulse Width Modulation (PWM) outputs
are possible. The PWMs use the TMR1 and TMR2
resources and the input Captures use the TMR3
resource.
10.1
Timer0 Overview
The Timer0 module is a simple 16-bit overow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock.
The Timer0 module also has a programmable pres-
caler option. The PS3:PS0 bits (T0STA<4:1>) deter-
mine the prescaler value. TMR0 can increment at the
following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64,
1:128, 1:256.
When TImer0’s clock source is an external clock, the
Timer0 module can be selected to increment on either
the rising or falling edge.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre-
quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
10.2
Timer1 Overview
The TImer0 module is an 8-bit timer/counter with an 8-
bit period register (PR1). When the TMR1 value rolls
over from the period match value to 0h, the TMR1IF
ag is set, and an interrupt will be generated when
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the Timer2 module.
TMR1 can be concatenated to TMR2 to form a 16-bit
timer. The TMR1 register is the LSB and TMR2 is the
MSB. When in the 16-bit timer mode, there is a corre-
sponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF ag is set, and an interrupt
will be generated when enabled.
10.3
Timer2 Overview
The TMR2 module is an 8-bit timer/counter with an 8-
bit period register (PR2). When the TMR2 value rolls
over from the period match value to 0h, the TMR2IF
ag is set, and an interrupt will be generated when
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the TMR1 module.
TMR1 can be concatenated to TMR2 to form a 16-bit
timer. The TMR2 register is the MSB and TMR1 is the
LSB. When in the 16-bit timer mode, there is a corre-
sponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF ag is set, and an interrupt
will be generated when enabled.
10.4
Timer3 Overview
The TImer3 module is a 16-bit timer/counter with a 16-
bit period register. When the TMR3H:TMR3L value
rolls over to 0h, the TMR3IF bit is set and an interrupt
will be generated when enabled. In counter mode, the
clock comes from the RB5/TCLK3 pin.
When operating in the dual capture mode, the period
registers become the second 16-bit capture register.
10.5
Role of the Timer/Counters
The timer modules are general purpose, but have ded-
icated resources associated with them. TImer1 and
Timer2 are the time-bases for the two Pulse Width
Modulation (PWM) outputs, while Timer3 is the time-
base for the two input captures.
This document was created with FrameMaker404
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