參數(shù)資料
型號: PIC17C43
英文描述: PIC17C42/42A/43/44/CR42A/CR43 Datasheet
中文描述: PIC17C42/42A/43/44/CR42A/CR43數(shù)據(jù)表
文件頁數(shù): 51/71頁
文件大小: 1173K
代理商: PIC17C43
1996 Microchip Technology Inc.
DS30412C-page 55
PIC17C4X
9.2
PORTB and DDRB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRB. A '1' in DDRB
congures the corresponding port pin as an input. A '0'
in the DDRB register congures the corresponding port
pin as an output. Reading PORTB reads the status of
the pins, whereas writing to it will write to the port latch.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
congured as an output. The pull-ups are enabled on
any reset.
PORTB also has an interrupt on change feature. Only
pins congured as inputs can cause this interrupt to
occur (i.e. any RB7:RB0 pin congured as an output is
excluded from the interrupt on change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch. The “mismatch” outputs
of RB7:RB0 are OR’ed together to generate the
PORTB Interrupt Flag RBIF (PIR<7>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt by:
a)
Read-Write PORTB (such as; MOVPF PORTB,
PORTB
). This will end mismatch condition.
b)
Then, clear the RBIF bit.
A mismatch condition will continue to set the RBIF bit.
Reading then writing PORTB will end the mismatch
condition, and allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with soft-
ware congurable pull-ups on this port, allows easy
interface to a key pad and make it possible for wake-up
on key-depression. For an example, refer to AN552 in
the
Embedded Control Handbook.
The interrupt on change feature is recommended for
wake-up on operations where PORTB is only used for
the interrupt on change feature and key depression
operation.
FIGURE 9-4:
BLOCK DIAGRAM OF RB<7:4> AND RB<1:0> PORT PINS
Note: I/O pins have protection diodes to VDD and VSS.
Data Bus
Q
D
CK
Q
D
CK
Weak
Pull-Up
Port
Input Latch
Port
Data
OE
WR_PORTB (Q4)
WR_DDRB (Q4)
RD_PORTB (Q2)
RD_DDRB (Q2)
RBIF
RBPU
Match Signal
from other
port pins
(PORTA<7>)
Peripheral Data in
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