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| 型號： | PIC17C43 |
| 英文描述： | PIC17C42/42A/43/44/CR42A/CR43 Datasheet |
| 中文描述： | PIC17C42/42A/43/44/CR42A/CR43數(shù)據(jù)表 |
| 文件頁數(shù)： | 14/71頁 |
| 文件大小： | 1173K |
| 代理商： | PIC17C43 |
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1996 Microchip Technology Inc.
DS30412C-page 21
PIC17C4X
5.0
INTERRUPTS
The PIC17C4X devices have 11 sources of interrupt:
External interrupt from the RA0/INT pin
Change on RB7:RB0 pins
TMR0 Overow
TMR1 Overow
TMR2 Overow
TMR3 Overow
USART Transmit buffer empty
USART Receive buffer full
Capture1
Capture2
T0CKI edge occurred
There are four registers used in the control and status
of interrupts. These are:
CPUSTA
INTSTA
PIE
PIR
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Memory Orga-
nization section.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specic
interrupt source (except the peripheral interrupts which
have the same vector address). These sources are:
External interrupt from the RA0/INT pin
TMR0 Overow
T0CKI edge occurred
Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupt address), the interrupt ag bit is automatically
cleared. Vectoring to the peripheral interrupt vector
address does not automatically clear the source of the
interrupt. In the peripheral interrupt service routine, the
source(s) of the interrupt can be determined by testing
the interrupt ag bits. The interrupt ag bit(s) must be
cleared in software before re-enabling interrupts to
avoid innite interrupt requests.
All of the individual interrupt ag bits will be set regard-
less of the status of their corresponding mask bit or the
GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the interrupt service routine.
When this instruction is executed, the stack is
“POPed”, and the GLINTD bit is cleared (to re-enable
interrupts).
FIGURE 5-1:
INTERRUPT LOGIC
TMR1IF
TMR1IE
TMR2IF
TMR2IE
TMR3IF
TMR3IE
CA1IF
CA1IE
CA2IF
CA2IE
TXIF
TXIE
RCIF
RCIE
RBIF
RBIE
T0IF
T0IE
INTF
INTE
T0CKIF
T0CKIE
GLINTD
PEIE
Wake-up (If in SLEEP mode)
or terminate long write
Interrupt to CPU
PEIF
This document was created with FrameMaker404
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| PIC17C43/JW | 功能描述:8位微控制器 -MCU 64KB 3328 RAM w/ECAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC17C43-16/L | 功能描述:8位微控制器 -MCU 8KB 454 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC17C43-16/L | 制造商:Microchip Technology Inc 功能描述:8BIT CMOS MCU SMD 17C43 PLCC44 |
| PIC17C43-16/P | 功能描述:8位微控制器 -MCU 8KB 454 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC17C43-16/P | 制造商:Microchip Technology Inc 功能描述:IC 8BIT CMOS MCU OTP 17C43 DIP40 |
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