參數(shù)資料
型號(hào)： PIC17C43
英文描述： PIC17C42/42A/43/44/CR42A/CR43 Datasheet
中文描述： PIC17C42/42A/43/44/CR42A/CR43數(shù)據(jù)表
文件頁(yè)數(shù)： 15/71頁(yè)
文件大?。?/td> 1173K
代理商： PIC17C43
PIC17C4X
DS30412C-page 22
1996 Microchip Technology Inc.
5.1
Interrupt Status Register (INTSTA)
The Interrupt Status/Control register (INTSTA) records
the individual interrupt requests in ag bits, and con-
tains the individual interrupt enable bits (not for the
peripherals).
The PEIF bit is a read only, bit wise OR of all the periph-
eral ag bits in the PIR register (Figure 5-4).
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA ag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).
When disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
Note:
T0IF, INTF, T0CKIF, or PEIF will be set by
the specied condition, even if the corre-
sponding interrupt enable bit is clear (inter-
rupt disabled) or the GLINTD bit is set (all
interrupts disabled).
FIGURE 5-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R - 0
R/W - 0 R/W - 0 R/W - 0
R/W - 0
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
bit0
bit 7:
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt ag bits AND’ed with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
bit 6:
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software specied edge occurred on the RA1/T0CKI pin
0 = The software specied edge did not occur on the RA1/T0CKI pin
bit 5:
T0IF: TMR0 Overow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 overowed
0 = TMR0 did not overow
bit 4:
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software specied edge occurred on the RA0/INT pin
0 = The software specied edge did not occur on the RA0/INT pin
bit 3:
PEIE: Peripheral Interrupt Enable bit
This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
bit 2:
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specied edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
bit 1:
T0IE: TMR0 Overow Interrupt Enable bit
1 = Enable TMR0 overow interrupt
0 = Disable TMR0 overow interrupt
bit 0:
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specied edge interrupt on the RA0/INT pin
0 = Disable software specied edge interrupt on the RA0/INT pin
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參數(shù)描述
PIC17C43/JW 功能描述:8位微控制器 -MCU 64KB 3328 RAM w/ECAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17C43-16/L 功能描述:8位微控制器 -MCU 8KB 454 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17C43-16/L 制造商:Microchip Technology Inc 功能描述:8BIT CMOS MCU SMD 17C43 PLCC44
PIC17C43-16/P 功能描述:8位微控制器 -MCU 8KB 454 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC17C43-16/P 制造商:Microchip Technology Inc 功能描述:IC 8BIT CMOS MCU OTP 17C43 DIP40
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