參數(shù)資料
型號(hào): PIC17C43
英文描述: PIC17C42/42A/43/44/CR42A/CR43 Datasheet
中文描述: PIC17C42/42A/43/44/CR42A/CR43數(shù)據(jù)表
文件頁數(shù): 41/71頁
文件大小: 1173K
代理商: PIC17C43
PIC17C4X
DS30412C-page 46
1996 Microchip Technology Inc.
7.2
Table Writes to External Memory
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
Note:
If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or T0CKI
interrupt ag is automatically cleared or
the
pending
peripheral
interrupt
is
acknowledged.
7.2.2
TABLE WRITE CODE
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically
incremented
for
the
next
write.
In
Example 7-1, the TBLPTR register is not automatically
incremented.
EXAMPLE 7-1:
TABLE WRITE
CLRWDT
; Clear WDT
MOVLW
HIGH (TBL_ADDR) ; Load the Table
MOVWF
TBLPTRH
;
address
MOVLW
LOW (TBL_ADDR)
;
MOVWF
TBLPTRL
;
MOVLW
HIGH (DATA)
; Load HI byte
TLWT
1, WREG
;
in TABLATCH
MOVLW
LOW (DATA)
; Load LO byte
TABLWT
0,0,WREG
;
in TABLATCH
;
and write to
;
program memory
;
(Ext. SRAM)
FIGURE 7-5:
TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4
AD15:AD0
Instruction
fetched
Instruction
executed
ALE
OE
WR
TABLWT
INST (PC+1)
INST (PC-1)
TABLWT cycle1
TABLWT cycle2
INST (PC+2)
Data write cycle
'1'
PC
PC+1
TBL
PC+2
Data out
INST (PC+1)
Note:
If external write GLINTD = '1', Enable bit = '1', '1'
→ Flag bit, Do table write. The highest pending interrupt is cleared.
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