參數(shù)資料
型號(hào): PIC12HV615
廠商: Microchip Technology Inc.
英文描述: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
中文描述: 8引腳閃存的基礎(chǔ)上,8位CMOS微控制器
文件頁數(shù): 98/168頁
文件大?。?/td> 1347K
代理商: PIC12HV615
PIC12F609/615/12HV609/615
DS41302A-page 96
Preliminary
2006 Microchip Technology Inc.
11.3.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
V
DD
has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to V
DD
. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
V
DD
is required. See
Section 15.0 “Electrical
Specifications”
for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until V
DD
reaches V
BOR
(see
Section 11.3.4 “Brown-out Reset
(BOR)”
).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN607,
“Power-up Trouble Shooting”
(DS00607).
11.3.2
PIC12F609/615/12HV609/615 has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to V
DD
. The use of an RC network, as shown in
Figure 11-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE =
0
, the Reset signal to the chip is generated
internally. When the MCLRE =
1
, the GP3/MCLR pin
becomes an external Reset input. In this mode, the
GP3/MCLR pin has a weak pull-up to V
DD
.
MCLR
FIGURE 11-2:
RECOMMENDED
MCLR
CIRCUIT
11.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from an internal
RC oscillator. For more information, see
Section 3.4
“Internal Clock Modes”
. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
V
DD
to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Reset is
enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
V
DD
variation
Temperature variation
Process variation
See DC parameters for details (
Section 15.0
“Electrical Specifications”
).
Note:
The POR circuit does not produce an
internal Reset when V
DD
declines. To re-
enable the POR, V
DD
must reach Vss for
a minimum of 100
μ
s.
Note:
Voltage spikes below V
SS
at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100
Ω
should be used when
applying a “l(fā)ow” level to the MCLR pin,
rather than pulling this pin directly to V
SS
.
V
DD
PIC
MCU
MCLR
R1
1 k
Ω (
or greater)
C1
0.1
μ
F
(optional, not critical)
R2
100
Ω
(
needed with capacitor)
SW1
(optional)
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