參數(shù)資料
型號： PIC12HV615
廠商： Microchip Technology Inc.
英文描述： 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
中文描述： 8引腳閃存的基礎(chǔ)上，8位CMOS微控制器
文件頁數(shù)： 80/168頁
文件大小： 1347K
代理商： PIC12HV615
PIC12F609/615/12HV609/615
DS41302A-page 78
Preliminary
2006 Microchip Technology Inc.
10.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 module may:
Toggle the CCP1 output.
Set the CCP1 output.
Clear the CCP1 output.
Generate a Special Event Trigger.
Generate a Software Interrupt.
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register.
All Compare modes can generate an interrupt.
FIGURE 10-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
10.2.1
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
CCP1 PIN CONFIGURATION
10.2.2
TIMER1 MODE SELECTION
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
10.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> =
1010
), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
10.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> =
1011
), the CCP1 module does the
following:
Resets Timer1
Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode (see the CCP1CON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
Q
S
R
Output
Logic
Special Event Trigger
Set CCP1IF Interrupt Flag
(PIR1)
4
Match
TRIS
Output Enable
CCP1CON<3:0>
Mode Select
Pin
Special Event Trigger will:
Clear TMR1H and TMR1L registers.
NOT set interrupt flag bit TMR1IF of the PIR1 register.
Set the GO/DONE bit to start the ADC conversion.
CCP1
Note 1:
The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMRxIF of the PIR1 register.
2:
Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
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參數(shù)描述
PIC12HV615-E/MD 功能描述:8位微控制器 -MCU 2KB Flash 64 RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC12HV615-E/MF 功能描述:8位微控制器 -MCU 1.75KB Flash 64B RAM 6 I/O 8MHz INT OSC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC12HV615-E/MS 功能描述:8位微控制器 -MCU 2KB Flash 64 RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC12HV615-E/P 功能描述:8位微控制器 -MCU 2KB Flash 64 RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC12HV615-E/SN 功能描述:8位微控制器 -MCU 2KB Flash 64 RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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