參數(shù)資料
型號: PIC12HV615
廠商: Microchip Technology Inc.
英文描述: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
中文描述: 8引腳閃存的基礎(chǔ)上,8位CMOS微控制器
文件頁數(shù): 58/168頁
文件大?。?/td> 1347K
代理商: PIC12HV615
PIC12F609/615/12HV609/615
DS41302A-page 56
Preliminary
2006 Microchip Technology Inc.
8.5
Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an
exclusive-or gate (see Figure 8-4 and Figure 8-5). One
latch is updated with the comparator output level when
the CMCON0 register is read. This latch retains the
value until the next read of the CMCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMCON0 register is read or the comparator output
returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the
interrupt flag can be reset without the additional step of
reading or writing the CMCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMCON1 register, to determine the actual change that
has occurred.
The CMIF bit of the PIR1 register is the Comparator
Interrupt flag. This bit must be reset in software by
clearing it to ‘
0
’. Since it is also possible to write a '
1
' to
this register, an interrupt can be generated.
The CMIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 register will still be set if an interrupt condition
occurs.
FIGURE 8-4:
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
FIGURE 8-5:
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
Note 1:
A write operation to the CMCON0 register
will also clear the mismatch condition
because all writes include a read opera-
tion at the beginning of the write cycle.
2:
Comparator interrupts will operate cor-
rectly regardless of the state of CMOE.
Note 1:
If a change in the CMCON0 register
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF of the PIR1
register interrupt flag may not get set.
2:
When a comparator is first enabled, bias
circuitry in the comparator module may
cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1
μ
s for bias settling
then clear the mismatch condition and
interrupt
flags
comparator interrupts.
before
enabling
Q1
Q3
CIN+
COUT
Set CMIF (edge)
CMIF
T
RT
reset by software
Q1
Q3
CIN+
COUT
Set CMIF (edge)
CMIF
T
RT
reset by software
cleared by CMCON0 read
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PIC12HV615-E/P 功能描述:8位微控制器 -MCU 2KB Flash 64 RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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