參數(shù)資料
型號(hào): PIC12F635T-E/SN
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO8
封裝: 0.150 INCH, PLASTIC, MS-012, SOIC-8
文件頁(yè)數(shù): 22/196頁(yè)
文件大?。?/td> 3291K
代理商: PIC12F635T-E/SN
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PIC12F635/PIC16F636/639
DS41232B-page 116
Preliminary
2005 Microchip Technology Inc.
12.7
Time-out Sequence
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC, while OST is active, by
enabling Two-Speed Start-up or Fail-Safe Clock Monitor
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F635/PIC16F636/
639 device operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
12.8
Power Control (PCON) Register
The Power Control register, PCON (address 8Eh), has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a Brown-out has occurred. The BOD Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BODEN<1:0> = 00 in the
Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 4.2.3 “Ultra Low-
TABLE 12-1:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 12-2:
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT DETECT
Oscillator
Configuration
Power-up
Brown-out Detect
Wake-up
from Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT + 1024 TOSC
1024 TOSC
TPWRT + 1024 TOSC
1024 TOSC
RC, EC, INTOSC
TPWRT
—TPWRT
——
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD,
WUR
Value on
all other
Resets(1)
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
8Eh
PCON
ULPWUE SBODEN
WUR
—POR
BOD
--01 q-qq
--0u u-uu
Legend:
u
= unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOD.
Note
1:
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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