- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299771 > PIC12F635T-E/SN 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO8 PDF資料下載
參數(shù)資料
| 型號： | PIC12F635T-E/SN |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, MS-012, SOIC-8 |
| 文件頁數(shù)： | 185/196頁 |
| 文件大小： | 3291K |
| 代理商： | PIC12F635T-E/SN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁當前第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁
2005 Microchip Technology Inc.
Preliminary
DS41232B-page 87
PIC12F635/PIC16F636/639
TABLE 11-1:
TYPICAL OUTPUT ENABLE
FILTER TIMING
TOEH is measured from the rising edge of the demodulator
output to the first falling edge. The pulse width must fall
within TOEH
≤ t ≤ TOET.
TOEL is measured from the falling edge of the
demodulator output to the rising edge of the next pulse.
The pulse width must fall within TOEL
≤ t ≤ TOET.
TOET is measured from rising edge to the next rising
edge (i.e., the sum of TOEH and TOEL). The pulse width
must be t
≤ TOET. If the Configuration Register 0
(Register 11-1), OEL<8:7> is set to ‘00’, then TOEH
must not exceed TOET and TOEL must not exceed
TINACT.
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions.
The received high is not greater than the
configured minimum TOEH value.
During TOEH, a loss of signal > 56
μs. A loss of
signal < 56
μs may or may not cause a filter
Reset.
The received low is not greater than the
configured minimum TOEL value.
The received sequence exceeds the maximum
TOET value:
-TOEH + TOEL > TOET
-or TOEH > TOET
-or TOEL > TOET
A Soft Reset SPI command is received.
If the filter resets due to a long high (TOEH > TOET), the
high-pulse timer will not begin timing again until after a
gap of TE and another low-to-high transition occurs on
the demodulator output.
Disabling the output enable filter disables the TOEH and
TOEL requirement and the AFE passes all received LF
data. See Figure 11-10, Figure 11-11 and Figure 11-12
for examples.
When viewed from an application perspective, from the
pin input, the actual output enable filter timing must fac-
tor in the analog delays in the input path (such as
demodulator charge and discharge times).
TOEH - TDR + TDF
TOEL + TDR - TDF
The output enable filter starts immediately after TGAP,
the gap after AGC stabilization period.
11.16 Input Sensitivity Control
The AFE is designed to have typical input sensitivity of
3mVPP. This means any input signal with amplitude
greater than 3 mVPP can be detected. The AFE’s internal
AGC loop regulates the detecting signal amplitude when
the input level is greater than approximately 20 mVPP.
This signal amplitude is called “AGC-active level”. The
AGC loop regulates the input voltage so that the input
signal amplitude range will be kept within the linear range
of the detection circuits without saturation. The AGC
Active Status bit (AGCACT<5>) in the AFE Status
Register 7 (Register 11-8) is set if the AGC loop
regulates the input voltage.
Table 11-2 shows the input sensitivity comparison when
the AGCSIG option is used. When AGCSIG option bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 11-1). The AFE has also
input sensitivity reduction options per each channel. The
Configuration Register 3 (Register 11-4), Configuration
Register 4 (Register 11-5) and Configuration Register 5
(Register 11-6) have the option to reduce the channel
gains from 0 dB to approximately -30 dB.
OEH
<1:0>
OEL
<1:0>
TOEH
(ms)
TOEL
(ms)
TOET
(ms)
01
00
11
3
01
11
3
01
10
12
4
01
11
14
6
10
00
21
4
10
01
21
4
10
22
5
10
11
24
8
11
00
41
6
11
01
41
6
11
10
42
8
11
44
10
00
XX
Filter Disabled
Note 1:
Typical at room temperature and
VDD = 3.0V, 32 kHz oscillator.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC16C65B-04I/PQ | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PQFP44 |
| PIC16C73BT-20E/SS | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO28 |
| PIC16C74B-04I/P | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP40 |
| PIC16LC73B-04I/SS | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| PIC16LC74B-04I/P | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC12F635T-I/MD | 功能描述:8位微控制器 -MCU 2 KB 64 RAM 6I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC12F635TI/MF | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY |
| PIC12F635T-I/MF | 功能描述:8位微控制器 -MCU 2kb 64 RAM 6 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC12F635TI/MFQTP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY |
| PIC12F635TI/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY |
發(fā)布緊急采購，3分鐘左右您將得到回復。