
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 62 of 77
June 10, 2005 Revision 1.06
8.1.59
NEXT CAPABILITIES POINTER REGISTER – OFFSET 90h
BIT
FUNCTION
TYPE
15:8
Next Capabilities
Pointer
DESCRIPTION
Next Capabilities Pointer
Returns 00h when read indicating that there are no more list items in
the capabilities list.
RO
8.1.60
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 90h
BIT
FUNCTION
TYPE
DESCRIPTION
31:27
PME# Pin Support
RO
PME# Pin Support
Returns 00000 when read designating that PI7C21P100 does not
support the PME# pin.
26
D2 Power State Support
RO
D2 Power State Support
Returns 0 when read indicating the D2 power management state is
not supported.
25
D1 Power State Support
RO
D1 Power State Support
Returns 0 when read indicating the D1 power management state is
not supported.
24:22
AUX Current
RO
AUX Current
Returns 000 when read indicating PME# generation is not supported
in the D3
cold
power management state.
21
Device Specific
Initialization
Returns 0 when read indicating that no special initialization of this
function beyond the standard PCI configuration header is required
following transition to the D0 un-initialized state.
20
RESERVED
RO
Reserved.
Returns 0 when read.
19
PME Clock
RO
PME Clock
Returns 0 when read indicating PME# generation is not supported.
18:16
Version
RO
Version
Returns 010 when read indicating PI7C21P100 complies with
revision 2.0 of the PCI Power Management Interface Specification.
RO
Device Specific Initialization
8.1.61
POWER MANAGEMENT CONTROL AND STATUS REGISTER –
OFFSET 94h
BIT
FUNCTION
TYPE
DESCRIPTION
15
PME Status
RO
PME Status
Returns 0 when read indicating PI7C21P100 does not support the
PME# pin.
14:13
Data Scale
RO
Data Scale
Returns 00 when read indicating the data register is not implemented.
12:9
Data Select
RO
Data Select
Returns 0000 when read indicating the data register is not
implemented.
8
PME Enable
RO
PME Enable
Returns 0 when read indication PME# generation is not supported.
7:2
RESERVED
RO
Reserved.
Returns 000000 when read.