
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 44 of 77
June 10, 2005 Revision 1.06
8.1.6
REVISION ID REGISTER – OFFSET 08h
BIT
FUNCTION
7:0
Revision ID
TYPE
RO
DESCRIPTION
Specifies the revision of PI7C21P100. Read as 0h
8.1.7
CLASS CODE REGISTER – OFFSET 08h
BIT
FUNCTION
31:24
Class Code
TYPE
RO
DESCRIPTION
Specifies the base class code for PI7C21P100 identifying it as a
Bridge device according to PCI specifications. Read as 06h
Specifies the sub-class code identifying PI7C21P100 as a Bridge
device. Read as 04h.
Subtractive decoding not supported. Read as 0h
23:16
Sub Class Code
RO
15:8
Programming Interface
RO
8.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch
BIT
FUNCTION
7:0
Cache Line Size
TYPE
RW
DESCRIPTION
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions. Not used in PCI-X mode.
bit[7:6]:
Not supported and should be 00b
bit[5]:
If 1, then cache line size = 32 DWORDS
bit[4]:
If 1, then cache line size = 16 DWORDS
bit[3]:
If 1, then cache line size = 8 DWORDS
bit[2]:
If 1, then cache line size = 4 DWORDS
bit[1:0]:
Not supported and should be 00b
8.1.9
PRIMARY LATENCY TIMER – OFFSET 0Ch
BIT
FUNCTION
15:11
Primary Latency Timer
TYPE
RW
DESCRIPTION
Designates the upper 5 bits of the primary latency timer in PCI clock
units
Designates the lower 3 bits of the primary latency timer in PCI clock
units. Returns 000 when read to force 8-cycle increments for the
latency timer.
10:8
Primary Latency Timer
RO
8.1.10
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
FUNCTION
23
Single Function Device
22:16
PCI-to-PCI
Configuration
TYPE
RO
RO
DESCRIPTION
Returns 0 when read to designate single function device
Returns 0000001 when read.
8.1.11
BIST REGISTER – OFFSET 0Ch
BIT
FUNCTION
31:24
BIST
TYPE
RO
DESCRIPTION
BIST not supported. Returns 0 when read.