
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 45 of 77
June 10, 2005 Revision 1.06
8.1.12
LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h
BIT
FUNCTION
TYPE
DESCRIPTION
31:20
Memory Base Address
RW
Address bits[31:20] of the memory base address if BAR_EN is 1. If
BAR_EN is 0, then this register is reserved and returns zeros when
read.
19:4
Reserved
RO
Reserved. Returns 00h when read
3
Prefetchable Indicator
RO
Identifies the address range defined by this register is prefetchable.
Returns 1 when read
2:1
Decoder Width
RO
Indicates that this is the lower portion of a 64-bit register. Returns
10b when read.
0
Decoder Type
RO
Indicates that this register is a memory decoder. Returns 0 when
read.
8.1.13
UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Upper Memory Base
Address
BAR_EN is 0, this register is reserved and returns zeros when read.
RW
Address bits[63:32] of the memory base address if BAR_EN is 1. If
8.1.14
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
7:0
Primary Bus Number
RW
DESCRIPTION
Records the bus number of the PCI segment that PI7C21P100 is
connected to on the primary side.
Reset to 00h
8.1.15
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
15:8
Secondary Bus Number
RW
DESCRIPTION
Records the bus number of the PCI segment that PI7C21P100 is
connected to on the secondary side.
Reset to 00h
8.1.16
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
23:16
Subordinate Bus
Number
DESCRIPTION
Records the highest bus number of the PCI segment that resides
behind PI7C21P100.
Reset to 00h
RW
8.1.17
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
31:24
Secondary Latency
Timer
DESCRIPTION
Specifies the value of the secondary latency timer in PCI bus clock
units.
Reset to 00h in conventional PCI mode
Reset to 40h in PCI-X mode
RW