參數(shù)資料
型號(hào)： PI7C21P100NH
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁(yè)數(shù)： 32/77頁(yè)
文件大小： 603K
代理商： PI7C21P100NH
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 32 of 77
June 10, 2005 Revision 1.06
The lowest two address bits on P_AD[1:0] are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the secondary
bus number register and the upper limit (inclusive) in the subordinate bus number
register.
P_AD[1:0] is a configuration read or configuration write transaction.
PI7C21P100 also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to support upstream special cycle generation. All upstream Type 1 configuration
read commands are ignored by PI7C21P100.
PI7C21P100 forwards Type 1 to Type 1 configuration read and write transactions as delayed
transactions in the PCI mode and as split transactions in PCI-X mode.
4.4.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in
hierarchical PCI/PCI-X systems. Special cycle transactions can be generated from Type 1
configuration write transactions in either the upstream or the downstream direction.
PI7C21P100 initiates a special cycle on the target bus when a Type 1 configuration write
transaction is detected on the initiating bus and the following conditions are met during the
address phase:
The lowest two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register for
downstream transactions or equal to the value in the primary bus number register for
upstream transactions.
The bus command on CBE is a configuration write command.
When PI7C21P100 initiates the transaction on the target interface, the bus command is
changed from configuration write to special cycle. Devices that use special cycles ignore the
address and decode only the bus command. The data phase contains the special cycle
message. The transaction is forwarded as a delayed transaction in PCI mode and as a split
transaction in PCI-X mode. Once the transaction is completed on the target bus through
detection of the master abort condition, PI7C21P100 completes the transaction on the
initiating bus by accepting the retry on the delayed command in PCI mode or by generating a
completion message in PCI-X mode. Special cycles received by PI7C21P100 as a target are
ignored.
5
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C21P100 complies with the ordering rules
set forth in the
PCI Local Bus Specification, Revision 2.2
for PCI mode, and
PCI-X
Addendum to the PCI Local Bus Specification, Revision 1.0a
for PCI-X mode. This chapter
describes the ordering rules that control transaction forwarding across PI7C21P100.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C21P100NHE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C4025TRF4 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C7100 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge
PI7C7100BNA 制造商:Pericom Semiconductor Corporation 功能描述:3 PORT PCI TO PCI
PI7C7100CNA 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge
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