參數(shù)資料
型號: PI7C21P100NH
廠商: Pericom Semiconductor Corp.
英文描述: 2-PORT PCI-X BRIDGE
中文描述: 2端口PCI - X橋接
文件頁數(shù): 47/77頁
文件大?。?/td> 603K
代理商: PI7C21P100NH
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 47 of 77
June 10, 2005 Revision 1.06
BIT
21
FUNCTION
66MHz Capable
TYPE
RO
DESCRIPTION
66MHz Capable Status
1:
Capable of 66MHz operation
Returns 1 when read.
Reserved.
Returns 00000 when read.
20:16
Reserved
RO
8.1.21
MEMORY BASE REGISTER – OFFSET 20h
BIT
FUNCTION
15:4
Memory Base
TYPE
RW
DESCRIPTION
Specifies the base of the memory mapped I/O address range
bit[31:20] and is used with the Memory Limit register to specify a
range of 32-bit addresses supported for memory mapped I/O
transactions.
Reset to 800h
Reserved. Returns 0 when read
3:0
Reserved
RO
8.1.22
MEMORY LIMIT REGISTER – OFFSET 20h
BIT
FUNCTION
31:20
Memory Limit
TYPE
RW
DESCRIPTION
Specifies address bits[31:20] of the limit address for the address
range of memory mapped I/O operations.
Reset to 000h
Reserved. Returns 0 when read
19:16
Reserved
RO
8.1.23
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
BIT
FUNCTION
TYPE
DESCRIPTION
15:4
Prefetchable Memory
Base
range of prefetchable memory operations.
Reset to 800h
3:0
64-bit Addressing
RO
Designates 64-bit addressing support. Returns 1h when read.
RW
Specifies address bits[31:20] of the base address for the address
8.1.24
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
BIT
FUNCTION
TYPE
DESCRIPTION
31:20
Prefetchable Memory
Limit
range of prefetchable memory operations.
Reset to 800h
19:16
64-bit Addressing
RO
Designates 64-bit addressing support. Returns 1h when read.
RW
Specifies address bits[31:20] of the limit address for the address
8.1.25
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Prefetchable Base
Upper 32-bit
range of prefetchable memory operations.
Reset to 0000 0000h
RW
Specifies address bits[63:32] of the base address for the address
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