
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 18 of 77
June 10, 2005 Revision 1.06
3.2.8
TEST SIGNALS
Name
T_DI1
Pin #
Y21
Type
IU
Description
PLL Bypass Control for PCI-X Mode.
The strapped
value of this pin (at P_RST# deassertion) controls
whether the internal PLL’s are bypassed in PCI-X mode.
HIGH: PLL’s are used in PCI-X mode
LOW: PLL’s are bypassed in PCI-X mode
Shorten Initialization Period.
Controls the period for
the following signals during initialization.
LOW: Shorten periods
T
PIRSTDLY
- 5 Primary Clocks
T
XCAP
– 6 Primary Clocks
T
SIRSTDLY
- 40 Secondary Clocks
T
SRSTDLY
– 11 Secondary Clocks + 7 Primary Clocks
HIGH: Normal initialization
T
PIRSTDLY
– See Table 7-2
T
XCAP
– See Table 7-2
T
SIRSTDLY
– See Table 7-2
T
SRSTDLY
– See Table 7-2
PLL Test Control.
Controls along with the internal
PLL testing.
T_RI
T_MODECTL
H
L
H
H
L
H
* P_PLL enabled, S_PLL disabled
**P_PLL disabled, S_PLL enabled
PLL Bypass Control for PCI Mode.
The strapped
value of this pin (at T_RI) controls whether the internal
PLL’s are bypassed in PCI mode.
1: PLL’s are bypassed in PCI mode
0 and T_MODECTL=0: PLL’s are used in PCI mode
Reserved.
Chip testing only. Tie LOW for normal
operation.
T_DI2
AA4
IU
T_MODECTL
T_RI
XCLK_OUT
C1
W22
D3
I
I
I
XCLK_OUT
Z
P_CLK*
S_CLK**
T_RI
W22
I
TEST_CE0
Y23
ID
3.2.9
POWER AND GROUND SIGNALS
Name
P_VDDA
Pin #
A21
Type
P
Description
2.5V Power:
Power supply to the PLL for the primary
clock domain.
2.5V Power:
Ground for the PLL for the primary clock
domain.
2.5V Power:
Power supply to the PLL for the secondary
clock domain.
2.5V Power:
Ground for the PLL for the secondary
clock domain.
2.5 Power:
Power supply for the internal logic
P_VSSA
D16
P
S_VDDA
AB21
P
S_VSSA
Y16
P
VDD
D9, D11, D13, D15,
J4, J20, L4, L20, N4,
N20, R4, R20, Y9,
Y11, Y13, Y15
P