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參數(shù)資料
| 型號： | PHD24N03 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TrenchMOS transistor Logic level FET |
| 中文描述： | TrenchMOS晶體管邏輯電平場效應(yīng)管 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 50K |
| 代理商： | PHD24N03 |
Philips Semiconductors
Preliminary specification
TrenchMOS
transistor
Logic level FET
PHD24N03LT
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C
.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 12 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
, C
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
0
5
10
15
20
PHP24N03LT
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS = 25 V
Tj = 25 C
175 C
0
-50
0
50
100
150
200
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
5
10
15
20
0
5
10
15
PHP24N03LT
Drain current, ID (A)
Transconductance, gfs (S)
VDS = 25 V
Tj = 25 C
175 C
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
-100
0
100
200
0
0.5
1
1.5
2
30V TrenchMOS
Tj / C
a
150
50
-50
1
10
100
1000
10
100
1000
PHP24N03LT
Drain-source voltage, VDS (V)
Capacitances Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
Tj = 25 C
December 1999
4
Rev 1.100
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