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參數(shù)資料
| 型號(hào)： | PHD24N03 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TrenchMOS transistor Logic level FET |
| 中文描述： | TrenchMOS晶體管邏輯電平場(chǎng)效應(yīng)管 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 50K |
| 代理商： | PHD24N03 |
Philips Semiconductors
Preliminary specification
TrenchMOS
transistor
Logic level FET
PHD24N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 30 V
’Trench’
technology
Very low on-state resistance
Fast switching
Stable off-state characteristics
High thermal cycling performance
Low thermal resistance
I
D
= 24 A
R
DS(ON)
≤
56 m
(V
GS
= 5 V)
R
DS(ON)
≤
50 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
PINNING
SOT428 (DPAK)
N-channel
logic
transistor in a plastic envelope
using ’
trench
’ technology. The
device
has
very
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
enhancement
level,
field-effect
mode,
power
PIN
DESCRIPTION
1
gate
low
on-state
2
drain
1
3
source
tab
drain
ThePHD24N03LTissuppliedinthe
SOT428 (DPAK) surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
13
24
20
96
60
175
UNIT
V
V
V
A
A
A
W
C
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
I
DM
P
D
T
j
, T
stg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
Thermal resistance junction
to mounting base
R
th j-a
Thermal resistance junction
to ambient
CONDITIONS
TYP.
-
MAX.
2.5
UNIT
K/W
pcb mounted, minimum footprint
50
-
K/W
d
g
s
1
2
3
tab
1
it is not possible to make connection to pin 2 of the SOT428 package.
December 1999
1
Rev 1.100
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| PHD24N03LT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TrenchMOS transistor Logic level FET |
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