參數(shù)資料
型號(hào)： PCD5013H
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： FLEX roaming decoder II
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù)： 65/76頁
文件大?。?/td> 270K
代理商： PCD5013H
1999 Apr 12
65
Philips Semiconductors
Product specification
FLEX
roaming decoder II
PCD5013
12 DC CHARACTERISTICS
T
amb
=
25 to +70
°
C; V
DD
= 2.2 V; f = 76.8 kHz; unless otherwise specified.
Notes
1.
External clock signal (frequency = 76.8 kHz, amplitude = V
SS
to V
DD
) at pin EXTAL; OSCPD = HIGH;
test inputs = LOW; other inputs = HIGH; outputs unconnected; SPI transmit enabled; COD bit set to logic 1 (see
Section 8.4.4); to obtain the supply current of an application with a crystal connected as in Fig.19, a typical oscillator
current of 2
μ
A needs to be added to this value (see Chapter 14); T
amb
= 25
°
C.
As note 1, but PCD5013 and synchronous to a typical FLEX
data stream (collapse value = 4), T
amb
= 25
°
C.
2.
13 AC CHARACTERISTICS
T
amb
=
25 to +70
°
C, V
DD
= 1.8 to 3.6 V, f
EXTAL
= 76.8 kHz, maximum load capacitance = 50 pF connected to any
digital output; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
I
DD(stby)
I
DD
supply voltage
standby supply current
operating supply current
1.8
2.2
4.9
6.0
3.6
24
V
μ
A
μ
A
on = 0; note 1
on = 1; note 2
Digital inputs: OSCPD, TEST2, TEST3, RESET, LOBAT, EXTS0, EXTS1, SS and MOSI
V
IL
V
IH
I
LI
LOW-level input voltage
HIGH-level input voltage
LOW/HIGH-level input leakage current
0.8V
DD
0.2V
DD
1
V
V
μ
A
Digital outputs: MISO, READY, CLKOUT, SYMCLK and S0 to S7
V
OL
V
OH
I
LO
LOW-level output voltage
HIGH-level output voltage
LOW/HIGH-level output leakage current 3-state outputs
I
sink
= 0.8 mA
I
source
=
0.8 mA
V
DD
0.4 V
DD
0.1
0.1
0.4
V
V
μ
A
1
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset timing
t
W(rst)
t
LH(RESET-READY)
t
HL(RESET-READY)
RESET pulse width
RESET LOW to READY HIGH
RESET HIGH to READY LOW stable 76.8 kHz clock
200
1
200
ns
ns
s
Start-up timing
t
strt(osc)
t
h(rst)
t
HL(RESET-READY)
t
WUL(osc-READY)
oscillator start-up time
RESET hold time
RESET HIGH to READY LOW note 1
oscillator warmed up to
READY LOW
see Fig.19
200
0.5
76800
76800
s
ns
T
T
note 1
SPI timing
f
SCK
T
cy(SCK)
t
LEAD1
t
LAG1
operating frequency
cycle time
select lead time
de-select lag time
0
1000
200
200
1
MHz
ns
ns
ns
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