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參數(shù)資料
| 型號： | PCD5013H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | FLEX roaming decoder II |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 32/76頁 |
| 文件大小： | 270K |
| 代理商： | PCD5013H |
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1999 Apr 12
32
Philips Semiconductors
Product specification
FLEX
roaming decoder II
PCD5013
8.5.6.2
Receiver on setting packets (ID = 16H to 19H)
LBC:
low battery check (Tables 24 and 25). If this bit is
set, the PCD5013 checks the status of the LOBAT port just
before leaving this receiver sync setting state. Value after
reset = 0.
CLS:
control line setting (Tables 24 and 25). This is the
value to be output on the receiver control lines for this
receiver sync setting state. Value after reset = 0.
ST:
step time (Table 24). This sets the waiting time, before
expecting good signals at EXTS1 and EXTS0 at the end of
the warm-up sequence, after turning decoding on.
The setting is in steps of 625
μ
s. Valid values are:
625
μ
s (ST = 01H) to 79.375 ms (ST = 7FH). Value after
reset = 01H.
s:
setting number, see Tables 23 and 25 for the s names
and values and location in the receiver on setting packet.
Table 23
s names and values
8.5.7
F
ORCING RECEIVER LINES
(ID = 0FH)
This packet (Table 26) enables host control over the
receiver control line (S0 to S7) settings in all modes except
reset. In reset, the receiver control lines are high
impedance.
FRS:
force receiver setting (Table 26). Setting a bit causes
the associated CLS bit in this packet to override the
internal receiver control settings on the corresponding
receiver control line. Clearing a bit returns control of the
corresponding receiver control line to the PCD5013. Value
after reset = 0.
CLS:
control line setting (Table 26). This bit setting is
applied to the corresponding receiver control line if the
associated FRS bit is set in this packet. Value after
reset = 0.
s
3
0
1
1
s
2
1
0
0
s
1
1
0
0
s
0
1
0
1
SETTING NAME
1600 sps sync
3200 sps data
1600 sps data
Table 24
3200 sps sync setting packet bit assignments
Table 25
Receiver on setting packet bit assignments
Table 26
Receiver line control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
LBC
CLS
3
ST
3
CLS
7
0
CLS
6
ST
6
CLS
5
ST
5
CLS
4
ST
4
CLS
2
ST
2
CLS
1
ST
1
CLS
0
ST
0
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
1
0
s
3
s
2
0
s
1
0
s
0
0
LBC
CLS
3
0
CLS
7
0
CLS
6
0
CLS
5
0
CLS
4
0
CLS
2
0
CLS
1
0
CLS
0
0
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
FRS
7
CLS
7
FRS
6
CLS
6
FRS
5
CLS
5
FRS
4
CLS
4
FRS
3
CLS
3
FRS
2
CLS
2
FRS
1
CLS
1
FRS
0
CLS
0
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