1999 Apr 12
44
Philips Semiconductors
Product specification
FLEX
roaming decoder II
PCD5013
8.7.7
S
HORT INSTRUCTION VECTOR
V:
these bits are set 001 for a short instruction vector.
WN:
word number of vector (2 to 87 decimal) (Table 46).
WN describes the location of the vector word in the frame.
e:
error (Table 46). Set if more than 2-bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
p:
phase (Table 46). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
i:
instruction type (Tables 46 and 47). These bits define
the meaning of the d bits in this packet.
x:
unused bits (Table 46). The value of these bits is not
guaranteed.
d:
data bits whose definition depend on the value of the
i bits in this packet according to Table 47. Note that if this
vector is received on a long address and the e bit in this
packet is not set, the decoder sends a message packet
immediately following the vector packet. All message bits
in the message packet are unused and should be ignored.
Table 46
Short instruction vector packet bit assignments
Table 47
Short instruction vector definitions
Notes
1.
2.
Assigned temporary address index a and associated frame number f (Section 8.8.5).
Refer to”FLEX
Protocol specification G1.9”.
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
e
x
d
4
WN
6
p
1
x
d
3
WN
5
p
0
d
10
d
2
WN
4
x
d
9
d
1
WN
3
x
d
8
d
0
WN
2
V
2
d
7
i
2
WN
1
V
1
d
6
i
1
WN
0
V
0
d
5
i
0
i
2
0
i
1
0
i
0
0
d
10
a
3
d
9
a
2
d
8
a
1
d
7
a
0
d
6
f
6
d
5
f
5
d
4
f
4
d
3
f
3
d
2
f
2
d
1
f
1
d
0
f
0
DESCRIPTION
temporary address assignment,
note 1
system event; note 2
temporary address with message
sequence number; note 2
reserved
reserved
reserved
reserved
reserved for test
0
0
0
1
1
0
d
10
a
3
d
9
a
2
d
8
a
1
d
7
a
0
d
6
f
6
d
5
N
5
d
4
N
4
d
3
N
3
d
2
N
2
d
1
N
1
d
0
N
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1